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[formal] Read Verilog files in Yosys

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All files read at this point should be Verilog and not SystemVerilog.
Do not use the SystemVerilog specifier for reading files.
This commit is contained in:
Tobias Wölfel 2021-07-13 08:59:55 +02:00 • committed by Rupert Swarbrick
parent e1eaa1c804
commit 7032df0d8b
1 changed files with 1 additions and 1 deletions
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2
formal/riscv-formal/Makefile
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@ -72,7 +72,7 @@ $(GEN_V): $(OUTDIR)%.v: $(SRC_DIR)%.sv $(PKGS) | $(OUTDIR)
# Combine multiple Verilog sources into one Ibex Verilog file # Combine multiple Verilog sources into one Ibex Verilog file
# Disable "M" extension # Disable "M" extension
$(IBEX_OUT): $(GEN_V) $(PRIM_CLOCK) $(IBEX_OUT): $(GEN_V) $(PRIM_CLOCK)
yosys -p "read_verilog -sv $(PRIM_CLOCK) $(GEN_V)" \ yosys -p "read_verilog $(PRIM_CLOCK) $(GEN_V)" \
-p "chparam -set RV32M 0 ibex_top" \ -p "chparam -set RV32M 0 ibex_top" \
-p "chparam -set WritebackStage $(IBEX_ENABLE_WB) ibex_top" \ -p "chparam -set WritebackStage $(IBEX_ENABLE_WB) ibex_top" \
-p "synth -top ibex_top" \ -p "synth -top ibex_top" \