mirror of
https://github.com/lowRISC/ibex.git
synced 2025-04-22 04:47:25 -04:00
Add parallelism to instr_gen_run and iss_sim steps
This commmit enables parallelism of more steps of the dv process by capturing the commands generated by the riscv-dv tool, then populating and executing a sub-makefile. This allows us to have parallelism at the level of the makefile jobserver. Seperated instr_gen build and run steps A python script construct_makefile.py is used to capture the raw output commands and construct a trivial makefile for each stage. This commit also renames some of the helper variables and stamps for consistency.
This commit is contained in:
Harry Callahan
Rupert Swarbrick
parent
9ba58db30a
commit
7083d669c6
2 changed files with 134 additions and 55 deletions
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@ -132,7 +132,7 @@ CSR_OPTS=--csr_yaml=${CSR_FILE} \
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--isa="${ISA}" \
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--end_signature_addr=${SIGNATURE_ADDR}
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RISCV_DV_OPTS=--custom_target=riscv_dv_extension \
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RISCV_DV_OPTS=--custom_target=$(realpath riscv_dv_extension)\
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--mabi=ilp32 \
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# To avoid cluttering the output directory with stamp files, we place them in
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@ -240,32 +240,34 @@ tests-and-seeds := \
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--iterations $(ITERATIONS) \
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--ibex-config $(IBEX_CONFIG))
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REGEX_EMPTY_LINES := '/^$$/d'
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###############################################################################
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# Generate random instructions
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###############################################################################
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# Build the Random Instruction Generator
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#
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# This depends on the vendored in code in $(GEN_DIR). It also depends on the
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# values of some variables (we want to regenerate things if, for example, the
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# simulator changes). Since we're writing out to $(OUT-SEED), we don't have to
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# depend on the value of SEED. However, we do have to make sure that the
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# variables whose names are listed in $(gen-var-deps) haven't changed.
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# variables whose names are listed in $(instr-gen-build-var-deps) haven't changed.
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#
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# To do this variable tracking, we dump each of the variables to a Makefile
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# fragment and try to load it up the next time around.
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gen-var-deps := GEN_OPTS SIMULATOR RISCV_DV_OPTS ISA CSR_OPTS \
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SIGNATURE_ADDR PMP_REGIONS PMP_GRANULARITY TEST_OPTS
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instr-gen-build-var-deps := GEN_OPTS SIMULATOR RISCV_DV_OPTS ISA CSR_OPTS \
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SIGNATURE_ADDR PMP_REGIONS PMP_GRANULARITY TEST_OPTS
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# Load up the generation stage's saved variable values. If this fails, that's
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# no problem: we'll assume that the previous run either doesn't exist or
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# something went wrong.
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-include $(metadata)/gen-vars.mk
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-include $(metadata)/.instr_gen.build.vars.mk
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# gen-vars-prereq is empty if every variable in gen-var-deps matches the last run,
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# otherwise it is set to FORCE (which will force a recompile). Note that we
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# define it with '=', not ':=', so we don't evaluate it if we're not trying to
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# run the gen target.
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gen-vars-prereq = \
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$(call vars-prereq,gen,building instruction generator,$(gen-var-deps))
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# instr-gen-build-vars-prereq is empty if every variable in
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# instr-gen-build-var-deps matches the last run, otherwise it is set to FORCE
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# (which will force a recompile). Note that we define it with '=', not ':=',
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# so we don't evaluate it if we're not trying to run the gen target.
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instr-gen-build-vars-prereq = \
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$(call vars-prereq,gen,building instruction generator,$(instr-gen-build-var-deps))
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# A variable containing a file list for the riscv-dv vendored-in module.
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# Depending on these files gives a safe over-approximation that will ensure we
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@ -276,38 +278,68 @@ gen-vars-prereq = \
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# than running it for every target otherwise.
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risc-dv-files := $(shell find $(GEN_DIR) -type f)
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# This actually runs the instruction generator. Note that the rule depends on
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# the (phony) FORCE target if any variables have changed. If the rule actually
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# runs, it starts by deleting any existing contents of $(OUT-SEED)/instr_gen.
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$(metadata)/instr_gen.gen.stamp: \
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$(gen-vars-prereq) $(risc-dv-files) $(TESTLIST) | $(metadata)
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# Note that the rule depends on the (phony) FORCE target if any variables have
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# changed. If the rule actually runs, it starts by deleting any existing
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# contents of $(OUT-SEED)/instr_gen.
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$(metadata)/.instr_gen.build.stamp: \
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$(instr-gen-build-vars-prereq) $(risc-dv-files) | $(metadata)
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$(verb)rm -rf $(OUT-SEED)/instr_gen
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$(verb)python3 ${GEN_DIR}/run.py \
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--co --steps=gen \
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--output=$(OUT-SEED)/instr_gen ${GEN_OPTS} \
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--steps=gen \
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--gen_timeout=${TIMEOUT} \
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--lsf_cmd="${LSF_CMD}" \
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--simulator="${SIMULATOR}" \
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${RISCV_DV_OPTS} \
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--isa=${ISA} \
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${CSR_OPTS}
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$(call dump-vars,$(metadata)/.instr_gen.build.vars.mk,gen,$(instr-gen-build-var-deps))
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@touch $@
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.PHONY: instr_gen_build
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instr_gen_build: $(metadata)/.instr_gen.build.stamp
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###############################################################################
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# Run the random instruction generator
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#
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RISCV_DV_ROOT := $(GEN_DIR)
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INSTR_GEN_RUN_COMMANDS := $(shell mktemp)
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$(metadata)/.instr_gen.run.stamp: \
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$(metadata)/.instr_gen.build.stamp \
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$(TESTLIST) | $(metadata)
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$(verb)rm -rf $(OUT-SEED)/instr_gen/asm_test
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@ # Generate the commands to be run into $(INSTR_GEN_RUN_COMMANDS)
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$(verb)python3 ${GEN_DIR}/run.py \
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--so --steps=gen \
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--output=$(OUT-SEED)/instr_gen ${GEN_OPTS} \
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--lsf_cmd="${LSF_CMD}" \
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--simulator="${SIMULATOR}" \
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--isa=${ISA} \
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${RISCV_DV_OPTS} \
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${TEST_OPTS} \
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${CSR_OPTS} \
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--sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,ibex_asm_program_gen,"uvm_test_top.asm_gen" \
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+signature_addr=${SIGNATURE_ADDR} +pmp_num_regions=${PMP_REGIONS} \
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+pmp_granularity=${PMP_GRANULARITY} +tvec_alignment=8"
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$(call dump-vars,$(metadata)/gen-vars.mk,gen,$(gen-var-deps))
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+pmp_granularity=${PMP_GRANULARITY} +tvec_alignment=8" \
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--debug $(INSTR_GEN_RUN_COMMANDS) # Write all the commands to execute into here...
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@ # Construct the sub-makefile from the commands, then call it
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@sed -i $(REGEX_EMPTY_LINES) $(INSTR_GEN_RUN_COMMANDS)
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$(verb)./construct_makefile.py \
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--output=$(OUT-SEED)/instr_gen/run.mk \
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--test_cmds=$(INSTR_GEN_RUN_COMMANDS)
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export RISCV_DV_ROOT
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@$(MAKE) -f $(OUT-SEED)/instr_gen/run.mk all
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@ # Bookkeeping
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@touch $@
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.PHONY: gen
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gen: $(metadata)/instr_gen.gen.stamp
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.PHONY: instr_gen_run
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instr_gen_run: $(metadata)/.instr_gen.run.stamp
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###############################################################################
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# Compile the generated assembly programs
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#
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# We don't explicitly track dependencies on the RISCV toolchain, so this
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# doesn't depend on anything more than the instr_gen stage did.
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$(metadata)/instr_gen.compile.stamp: \
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$(metadata)/instr_gen.gen.stamp $(TESTLIST)
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$(metadata)/.instr_gen.compile_tests.stamp: \
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$(metadata)/.instr_gen.run.stamp $(TESTLIST)
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$(verb)python3 ${GEN_DIR}/run.py \
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--o=$(OUT-SEED)/instr_gen ${GEN_OPTS} \
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--steps=gcc_compile \
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@ -317,8 +349,8 @@ $(metadata)/instr_gen.compile.stamp: \
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--isa=${ISA} && \
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touch $@
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.PHONY: gcc_compile
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gcc_compile: $(metadata)/instr_gen.compile.stamp
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.PHONY: instr_gen_compile
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instr_gen_compile: $(metadata)/.instr_gen.compile_tests.stamp
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###############################################################################
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# Run the instruction set simulator
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@ -328,11 +360,13 @@ gcc_compile: $(metadata)/instr_gen.compile.stamp
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# ISS and ISS_OPTS variables do affect the output, so we need to dump them. See
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# the 'gen' stage for more verbose explanations of how this works.
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iss-var-deps := ISS ISS_OPTS
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-include $(metadata)/iss-vars.mk
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-include $(metadata)/.iss.vars.mk
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iss-vars-prereq = $(call vars-prereq,iss,running ISS,$(iss-var-deps))
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$(metadata)/instr_gen.iss.stamp: \
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$(iss-vars-prereq) $(TESTLIST) $(metadata)/instr_gen.compile.stamp
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ISS_COMMANDS := $(shell mktemp)
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$(metadata)/.iss.run.stamp: \
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$(metadata)/.instr_gen.compile_tests.stamp $(iss-vars-prereq) $(TESTLIST)
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@ # Generate the commands to be run into $(ISS_COMMANDS)
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$(verb)python3 ${GEN_DIR}/run.py \
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--o=$(OUT-SEED)/instr_gen ${GEN_OPTS} \
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--steps=iss_sim \
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@ -340,12 +374,20 @@ $(metadata)/instr_gen.iss.stamp: \
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--iss="${ISS}" \
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--iss_opts="${ISS_OPTS}" \
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--isa="${ISA_ISS}" \
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${RISCV_DV_OPTS}
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$(call dump-vars,$(metadata)/iss-vars.mk,iss,$(iss-var-deps))
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${RISCV_DV_OPTS} \
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--debug $(ISS_COMMANDS) # Write all the commands to execute into here...
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@ # Construct the sub-makefile from the commands, then call it
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@sed -i $(REGEX_EMPTY_LINES) $(ISS_COMMANDS)
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$(verb)./construct_makefile.py \
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--output=$(OUT-SEED)/instr_gen/iss.mk \
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--test_cmds=$(ISS_COMMANDS)
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@$(MAKE) -f $(OUT-SEED)/instr_gen/iss.mk all
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@ # Bookkeeping
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$(call dump-vars,$(metadata)/.iss.vars.mk,iss,$(iss-var-deps))
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@touch $@
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.PHONY: iss_sim
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iss_sim: $(metadata)/instr_gen.iss.stamp
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.PHONY: iss_run
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iss_run: $(metadata)/.iss.run.stamp
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###############################################################################
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@ -355,7 +397,7 @@ iss_sim: $(metadata)/instr_gen.iss.stamp
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# doesn't depend on which test we're running!
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#
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# It does, however, depend on various variables. These are listed in
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# compile-var-deps. See the 'gen' stage for more verbose explanations of how
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# tb-compile-var-deps. See the 'gen' stage for more verbose explanations of how
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# the variable dumping works.
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#
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# The compiled ibex testbench (obviously!) also depends on the design and the
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@ -370,19 +412,19 @@ all-verilog = \
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$(shell find ../../../rtl -name '*.v' -o -name '*.sv' -o -name '*.svh') \
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$(shell find ../.. -name '*.v' -o -name '*.sv' -o -name '*.svh')
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compile-var-deps := COMMON_OPTS SIMULATOR COV WAVES COMPILE_OPTS COSIM
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-include $(OUT-DIR)rtl_sim/.compile-vars.mk
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compile-vars-prereq = $(call vars-prereq,comp,compiling TB,$(compile-var-deps))
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tb-compile-var-deps := COMMON_OPTS SIMULATOR COV WAVES COMPILE_OPTS COSIM
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-include $(OUT-DIR)rtl_sim/.rtl.tb_compile.vars.mk
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tb-compile-vars-prereq = $(call vars-prereq,comp,compiling TB,$(tb-compile-var-deps))
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$(call dump-vars-match,$(compile-var-deps),comp)
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$(call dump-vars-match,$(tb-compile-var-deps),comp)
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cov-arg := $(if $(call equal,$(COV),1),--en_cov,)
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wave-arg := $(if $(call equal,$(WAVES),1),--en_wave,)
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cosim-arg := $(if $(call equal,$(COSIM),1),--en_cosim,)
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lsf-arg := $(if $(LSF_CMD),--lsf_cmd="$(LSF_CMD)",)
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$(OUT-DIR)rtl_sim/.compile.stamp: \
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$(compile-vars-prereq) $(all-verilog) $(risc-dv-files) \
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$(OUT-DIR)rtl_sim/.rtl.tb_compile.stamp: \
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$(tb-compile-vars-prereq) $(all-verilog) $(risc-dv-files) \
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sim.py yaml/rtl_simulation.yaml \
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| $(OUT-DIR)rtl_sim
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$(verb)./sim.py \
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@ -392,11 +434,11 @@ $(OUT-DIR)rtl_sim/.compile.stamp: \
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--simulator="${SIMULATOR}" --simulator_yaml=yaml/rtl_simulation.yaml \
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$(cov-arg) $(wave-arg) $(cosim-arg) $(lsf-arg) \
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--cmp_opts="${COMPILE_OPTS}"
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$(call dump-vars,$(OUT-DIR)rtl_sim/.compile-vars.mk,comp,$(compile-var-deps))
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$(call dump-vars,$(OUT-DIR)rtl_sim/.rtl.tb_compile-vars.mk,comp,$(tb-compile-var-deps))
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@touch $@
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.PHONY: compile
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compile: $(OUT-DIR)rtl_sim/.compile.stamp
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.PHONY: rtl_tb_compile
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rtl_tb_compile: $(OUT-DIR)rtl_sim/.rtl.tb_compile.stamp
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###############################################################################
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# Run ibex RTL simulation with generated programs
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@ -406,11 +448,12 @@ compile: $(OUT-DIR)rtl_sim/.compile.stamp
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# running the test) dependent on having the right variables. That way, we'll
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# correctly delete the sim directory and re-copy it if necessary.
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#
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# Note that the variables we depend on are gen-vars-prereq. We also depend on
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# COV and WAVES, but these dependencies will come for free from the dependency
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# on the compiled TB.
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$(metadata)/rtl_sim.compile.stamp: \
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$(gen-vars-prereq) $(risc-dv-files) $(OUT-DIR)rtl_sim/.compile.stamp
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# Note that the variables we depend on are instr-gen-build-vars-prereq.
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# We also depend on COV and WAVES, but these dependencies will come for free
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# from the dependency on the compiled TB.
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$(metadata)/.rtl.tb_compile.stamp: \
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$(OUT-DIR)rtl_sim/.rtl.tb_compile.stamp \
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$(instr-gen-build-vars-prereq) $(risc-dv-files)
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rm -rf $(OUT-SEED)/rtl_sim
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cp -r $(OUT-DIR)rtl_sim $(OUT-SEED)
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@touch $@
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@ -420,8 +463,8 @@ rtl-sim-logs := $(addsuffix /sim.log,$(rtl-sim-dirs))
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$(rtl-sim-logs): \
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%/sim.log: \
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$(metadata)/rtl_sim.compile.stamp \
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$(metadata)/instr_gen.compile.stamp \
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$(metadata)/.rtl.tb_compile.stamp \
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$(metadata)/.instr_gen.compile_tests.stamp \
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run_rtl.py
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@echo Running RTL simulation at $@
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$(verb)mkdir -p $(@D)
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@ -435,8 +478,8 @@ $(rtl-sim-logs): \
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--bin-dir $(OUT-SEED)/instr_gen/asm_test \
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--rtl-sim-dir $(OUT-SEED)/rtl_sim
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.PHONY: rtl_sim
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rtl_sim: $(rtl-sim-logs)
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.PHONY: rtl_sim_run
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rtl_sim_run: $(rtl-sim-logs)
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###############################################################################
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# Compare ISS and RTL sim results
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@ -456,7 +499,8 @@ comp-results := $(addsuffix /test-result.yml,$(rtl-sim-dirs))
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$(comp-results): \
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%/test-result.yml: \
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compare.py $(metadata)/instr_gen.iss.stamp $(rtl-sim-logs)
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$(metadata)/.iss.run.stamp \
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$(rtl-sim-logs) compare.py
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@echo Comparing traces for $*
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$(verb)./compare.py \
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--instr-gen-bin-dir $(OUT-SEED)/instr_gen/asm_test \
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35
dv/uvm/core_ibex/construct_makefile.py
Executable file
35
dv/uvm/core_ibex/construct_makefile.py
Executable file
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@ -0,0 +1,35 @@
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#!/usr/bin/env python3
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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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import argparse
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import os
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import sys
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_CORE_IBEX = os.path.normpath(os.path.join(os.path.dirname(__file__)))
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_IBEX_ROOT = os.path.normpath(os.path.join(_CORE_IBEX, '../../..'))
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_RISCV_DV_ROOT = os.path.join(_IBEX_ROOT, 'vendor/google_riscv-dv')
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_OLD_SYS_PATH = sys.path
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def main() -> int:
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parser = argparse.ArgumentParser()
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parser.add_argument('--test_cmds', required=True)
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parser.add_argument('--output', required=True)
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args = parser.parse_args()
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with open(args.test_cmds) as f, \
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open(args.output, 'w', encoding='UTF-8') as outfile:
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for i, line in enumerate(f):
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outfile.write(f'{i}:\n')
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outfile.write('\t' + line)
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outfile.write(f'CMDS := $(shell seq 0 {i})\n')
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outfile.write('all: $(CMDS)')
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return 0
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if __name__ == '__main__':
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sys.exit(main())
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