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[fcov, doc] Update coverage plan
Added coverpoint and cross names to relevant plan entries so plan is up to date with implemented coverage. Also some minor changes to remove plan entries that are no longer required.
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Greg Chadwick
Greg Chadwick
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1 changed files with 30 additions and 25 deletions
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@ -32,7 +32,7 @@ Instructions
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Categories
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""""""""""
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``cp_instr_category_id``
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``cp_id_instr_category``
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Instructions can be grouped into a number of categories.
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Each category exercises different data and control paths in the core.
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@ -105,11 +105,12 @@ Privilege Level
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Ibex can operate at either the M (machine) or U (user) privilege levels.
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Different aspects of the Ibex microarchitecture can be using different privilege levels at once.
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* ``cp_priv_mode_if`` - Privilege level of IF stage instruction.
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* ``cp_priv_mode_id`` - Privilege level of ID/EX stage instruction.
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* ``cp_priv_mode_lsu`` - Privilege level of LSU operation (ID/EX privilege level modified by ``mstatus.mprv`` and ``mstatus.mpp`` settings).
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Note that the privilege level of the instruction in WB isn't retained by the microarchitecture and is not relevant to coverage.
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The privilege level of the IF instruction is effectively unknown.
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The instruction is checked when moving from IF to ID/EX against the ID stage privilege level to check if execution is permitted by PMP.
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Any instruction that reaches WB can be considered bound to retire and any relevant checks and functionality altered by the privilege mode is dealt with at an earlier stage.
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Hazards
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@ -133,14 +134,14 @@ Some instructions will behave differently depending upon the state of the proces
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* Instruction illegal in U Mode.
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* ``MRET`` - ``cp_mret_in_umode``
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* ``WFI`` - ``cp_wfi_in_umode``
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* Read and write to M-mode CSR - Covered by crosses ``csr_wr_priv_cross`` and ``csr_rd_only_priv_cross```
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* ``cp_mret_in_umode`` - ``MRET``
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* ``cp_wfi_in_umode`` - ``WFI``
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* Read and write to M-mode CSR - Covered by crosses ``csr_write_priv_cross`` and ``csr_read_only_priv_cross```
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* Debug mode instructions (cover execution in and out of debug mode).
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* ``DRET``
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* Access to debug CSRs.
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* ``csr_read_only_debug_cross``, ``csr_write_debug_cross`` - Access to debug CSRs.
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* ``dcsr``
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* ``dpc``
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@ -148,16 +149,16 @@ Some instructions will behave differently depending upon the state of the proces
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* ``dscratch1``
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* Access to trigger CSRs (also possible in M mode: cover execution in M mode, debug mode and U mode).
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Covered by ``csr_read_only_debug_cross``, ``csr_write_debug_cross``, ``csr_read_only_priv_cross``, ``csr_write_priv_cross``.
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* ``tselect``
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* ``tdata1``
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* ``tdata2``
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* ``tdata3``
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* ``mcontext``
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* ``scontext``
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* Loads/stores with ``mstatus.mprv`` set and unset.
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* EBreak behaviour in U/M mode with different ``dcsr.ebreakm`` / ``dcsr.ebreaku`` settings.
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Covered by ``priv_mode_instr_cross``
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Pipeline State
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^^^^^^^^^^^^^^
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@ -169,7 +170,7 @@ Each pipeline stage has some associated state.
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* ``cp_id_stage_state`` - ID stage full and stalled, full and unstalled, or empty.
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* Controller (within ID stage) state machine states
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* Possible transitions between these states.
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* ``cp_controller_fsm`` - Possible transitions between these states.
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Those marked with a '*' are of particular interest and should be crossed with instruction categories and other coverpoints as appropriate to fully explore the transitions.
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* ``RESET`` -> ``BOOT_SET``
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@ -229,8 +230,10 @@ PMP
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* Access fail & pass.
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* All combinations of unaligned access split across a boundary, both halves pass, neither pass, just the first passes, just the second passes.
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* Two possible boundary splits; across a 32-bit boundary within a region or a boundary between PMP regions.
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* ``cp_pmp_iside_region_override`` / ``cp_pmp_dside_region_override`` - Higher priority entry allows access that lower priority entry prevents.
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* ``cp_pmp_iside_region_override``, ``cp_pmp_iside2_region_override``, ``cp_pmp_dside_region_override`` - Higher priority entry allows access that lower priority entry prevents.
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* Compressed instruction access (16-bit) passes PMP but 32-bit access at same address crosses PMP region boundary.
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* Each field of mssecfg enabled/disabled with relevant functionality tested.
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@ -267,7 +270,7 @@ Basic read/write functionality must be tested on all implemented CSRs.
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* Access to CSR disallowed due to privilege levels/debug mode
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Covered by ensuring within the crosses
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* ``cp_invalid_read_only`` / ``cp_invalid_write`` - Read and write from/to an unimplemented CSR
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* ``cp_invalid_read_only``, ``cp_invalid_write`` - Read and write from/to an unimplemented CSR
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CSRs addresses do not need to be crossed with the variety of CSR instructions as these all use the same basic read & write interface into ``ibex_cs_registers``.
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Coverage of the above points will be sampled at the ``ibex_cs_registers`` interface (as opposed to sampling CSR instructions).
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@ -276,10 +279,9 @@ Miscellaneous
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^^^^^^^^^^^^^
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Various points of interest do not fit into the categories above.
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* Instruction unstalled - Cover the cycle an instruction is unstalled having just been stalled.
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* Stalled awaiting an instruction fetch.
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* ``instr_unstalled`` - Instruction unstalled - Cover the cycle an instruction is unstalled having just been stalled.
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* Double fault.
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* Awake from sleep.
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* Awake from sleep due to interrupt or debug
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* Interrupt/Debug whilst entering sleep.
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* Enabling/Disabling ICache.
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@ -287,6 +289,7 @@ Cross Coverage
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--------------
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Much of the more complex behaviour lies at the combination of the individual microarchitectural behaviours above.
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Cross coverage is used to capture that.
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Crosses listed below are ones that don't already fit into the above categories.
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There are some broad crosses containing many bins aiming to capture all combinations of some generalised behaviours as well as some more specific ones to capture all combinations of behaviours focused on a particular area.
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Cross coverage will be intentionally broad.
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@ -295,30 +298,32 @@ Where it is proving hard to hit particular bins they will be reviewed in more de
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Excluded bins will either become illegal bins (where they are impossible to hit, so a failure will be seen if they are hit) or ignore bins (where they don't factor into coverage statistics).
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There must be a documented reason a particular bin is added to the illegal or ignore bins.
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* All combinations of privilege levels across IF, ID/EX and LSU
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* Instruction Categories x Pipeline stage states across IF, ID/EX and WB
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* ``pipe_cross`` - Instruction Categories x Pipeline stage states across IF, ID/EX and WB
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* Covers all possibilities of instruction combinations that could fill the pipeline. State only for IF/WB suffices to cover this as all the interesting per instruction behaviour occurs in ID/EX.
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* All bins containing instruction categories other than **None** ignored when ID/EX stage is empty.
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* Instructions Categories x ID/EX Privilege level
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* Instruction Categories x Stall Categories
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* ``priv_mode_instr_cross`` - Instructions Categories x ID/EX Privilege level
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* ``stall_cross`` - Instruction Categories x Stall Categories
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* Illegal bins will be used to exclude instruction and stall categories that cannot occur.
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* Instruction Categories x Hazards
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* Instruction Categories x Debug Mode
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* Instruction Categories x IF/WB full or empty
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* ``wb_reg_no_load_hz_instr_cross`` - Instruction Categories x Hazards
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* ``stall_cross`` covers the RAW load hazard (as it produces a LdHz stall).
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* RAW hazard between load/store requires no cross coverage as it's only seen for load and store instructions so the single coverpoint suffices.
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* ``debug_instruction_cross`` - Instruction Categories x Debug Mode
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* Instruction Categories x Controller state transitions of interest
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* Interrupt taken/Debug mode entry/Pipe flush x instruction unstalled x instruction category
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* ``interrupt_taken_instr_cross``, ``debug_entry_if_instr_cross``, ``pipe_flush_instr_cross`` - Interrupt taken/Debug mode entry/Pipe flush x instruction unstalled x instruction category
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* Three separate cross coverage groups: one for interrupt, debug and pipe flush.
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* Covers all instruction categories being interrupted/entering debug mode/flushing the pipeline both where this occurs during a stall and when it occurs just when they've unstalled.
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* PMP exception x load/store error exception x instruction category x stall type x unstalled x irq pending x debug req
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* ``exception_stall_instr_cross`` - PMP exception x load/store error exception x instruction category x stall type x unstalled x irq pending x debug req
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* Large cross to cover all possibilities of combinations between interrupt, debug and exceptions for all instruction categories across all stall behaviours.
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* PMP regions x permissions x access fail/pass x privilege level
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* ``pmp_iside_priv_bits_cross``, ``pmp_iside2_priv_bits_cross``, ``pmp_dside_priv_bits_cross``, PMP regions x permissions x access fail/pass x privilege level
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* Two crosses, one for each PMP channel (instruction and data).
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* Three crosses, one for each PMP channel (instruction, instruction 2 and data).
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