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[doc] Remove area result specifics from Ibex overview

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Area consumed varies by configuration and will change as the Ibex RTL
changes. So reporting area numbers within documentation is not
sensible.
This commit is contained in:
Greg Chadwick 2023-01-27 15:20:32 +00:00 • committed by Greg Chadwick
parent 91d641cebf
commit 77cd6e4dda
1 changed files with 0 additions and 2 deletions
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doc/01_overview/targets.rst
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@ -7,8 +7,6 @@ ASIC Synthesis
ASIC synthesis is supported for Ibex.
The whole design is completely synchronous and uses positive-edge triggered flip-flops, except for the register file, which can be implemented either with latches or with flip-flops.
See :ref:`register-file` for more details.
The core occupies an area of roughly 24 kGE when using the latch-based register file and implementing the RV32IMC ISA, or 15 kGE when implementing the RV32EC ISA.
FPGA Synthesis
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