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Add missing MUL_SUPPORT directives
This commit is contained in:
Markus Wegmann
parent
bd0728a8d9
commit
783eeb6172
3 changed files with 64 additions and 3 deletions
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@ -24,6 +24,8 @@
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "riscv_config.sv"
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import riscv_defines::*;
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module riscv_controller
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@ -61,8 +63,11 @@ module riscv_controller
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input logic data_misaligned_i,
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input logic data_load_event_i,
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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// from ALU
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input logic mult_multicycle_i, // multiplier is taken multiple cycles and uses op c as storage
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`ifndef
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// jump/branch signals
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input logic branch_taken_ex_i, // branch taken signal from EX ALU
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@ -555,9 +560,13 @@ module riscv_controller
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begin
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operand_a_fw_mux_sel_o = SEL_FW_EX;
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operand_b_fw_mux_sel_o = SEL_REGFILE;
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end else if (mult_multicycle_i) begin
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end
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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else if (mult_multicycle_i) begin
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operand_c_fw_mux_sel_o = SEL_FW_EX;
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end
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`endif
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end
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// update registers
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@ -24,6 +24,8 @@
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "riscv_config.sv"
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import riscv_defines::*;
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module riscv_decoder
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@ -31,7 +33,10 @@ module riscv_decoder
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// singals running to/from controller
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input logic deassert_we_i, // deassert we, we are stalled or not active
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input logic data_misaligned_i, // misaligned data load/store in progress
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`ifdef MUL_SUPPORT
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// MUL related control signals
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input logic mult_multicycle_i, // multiplier taking multiple cycles, using op c as storage
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`endif // MUL_SUPPORT
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output logic illegal_insn_o, // illegal instruction encountered
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output logic ebrk_insn_o, // trap instruction encountered
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51
id_stage.sv
51
id_stage.sv
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@ -25,6 +25,7 @@
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// //
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////////////////////////////////////////////////////////////////////////////////
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`include "riscv_config.sv"
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import riscv_defines::*;
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@ -108,6 +109,8 @@ module riscv_id_stage
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output logic [ALU_OP_WIDTH-1:0] alu_operator_ex_o,
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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// MUL
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output logic [ 2:0] mult_operator_ex_o,
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output logic [31:0] mult_operand_a_ex_o,
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@ -122,6 +125,8 @@ module riscv_id_stage
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output logic [31:0] mult_dot_op_b_ex_o,
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output logic [31:0] mult_dot_op_c_ex_o,
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output logic [ 1:0] mult_dot_signed_ex_o,
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`endif // MUL_SUPPORT
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// CSR ID/EX
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output logic csr_access_ex_o,
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@ -190,8 +195,11 @@ module riscv_id_stage
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input logic regfile_alu_we_fw_i,
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input logic [31:0] regfile_alu_wdata_fw_i,
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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// from ALU
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input logic mult_multicycle_i, // when we need multiple cycles in the multiplier and use op c as storage
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`endif // MUL_SUPPORT
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// Performance Counters
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output logic perf_jump_o, // we are executing a jump instruction
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@ -278,6 +286,8 @@ module riscv_id_stage
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logic [3:0] imm_b_mux_sel;
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logic [1:0] jump_target_mux_sel;
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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// Multiplier Control
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logic [2:0] mult_operator; // multiplication operation selection
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logic mult_en; // multiplication is used instead of ALU
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@ -286,6 +296,7 @@ module riscv_id_stage
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logic [1:0] mult_signed_mode; // Signed mode multiplication at the output of the controller, and before the pipe registers
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logic mult_dot_en; // use dot product
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logic [1:0] mult_dot_signed; // Signed mode dot products (can be mixed types)
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`endif // MUL_SUPPORT
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// Register Write Control
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logic regfile_we_id;
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@ -336,12 +347,18 @@ module riscv_id_stage
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// Immediates for ID
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logic [0:0] bmask_a_mux;
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logic [1:0] bmask_b_mux;
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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logic [0:0] mult_imm_mux;
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`endif // MUL_SUPPORT
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logic [ 4:0] bmask_a_id;
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logic [ 4:0] bmask_b_id;
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logic [ 1:0] imm_vec_ext_id;
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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logic [ 4:0] mult_imm_id;
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`endif // MUL_SUPPORT
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logic [ 1:0] alu_vec_mode;
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logic scalar_replication;
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@ -433,8 +450,10 @@ module riscv_id_stage
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assign branch_taken_ex = branch_in_ex_o & branch_decision_i;
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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assign mult_en = mult_int_en | mult_dot_en;
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`endif // MUL_SUPPORT
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///////////////////////////////////////////////
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// _ ___ ___ ___ ___ ____ //
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@ -682,6 +701,8 @@ module riscv_id_stage
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assign imm_vec_ext_id = imm_vu_type[1:0];
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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always_comb
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begin
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unique case (mult_imm_mux)
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@ -690,6 +711,7 @@ module riscv_id_stage
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default: mult_imm_id = '0;
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endcase
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end
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`endif // MUL_SUPPORT
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/////////////////////////////////////////////////////////
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// ____ _____ ____ ___ ____ _____ _____ ____ ____ //
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@ -746,7 +768,11 @@ module riscv_id_stage
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// controller related signals
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.deassert_we_i ( deassert_we ),
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.data_misaligned_i ( data_misaligned_i ),
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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.mult_multicycle_i ( mult_multicycle_i ),
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`endif // MUL_SUPPORT
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.illegal_insn_o ( illegal_insn_dec ),
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.ebrk_insn_o ( ebrk_insn ),
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@ -777,6 +803,8 @@ module riscv_id_stage
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.imm_b_mux_sel_o ( imm_b_mux_sel ),
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.regc_mux_o ( regc_mux ),
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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// MUL signals
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.mult_operator_o ( mult_operator ),
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.mult_int_en_o ( mult_int_en ),
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@ -785,6 +813,7 @@ module riscv_id_stage
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.mult_imm_mux_o ( mult_imm_mux ),
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.mult_dot_en_o ( mult_dot_en ),
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.mult_dot_signed_o ( mult_dot_signed ),
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`endif // MUL_SUPPORT
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// Register file control signals
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.regfile_mem_we_o ( regfile_we_id ),
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@ -861,8 +890,11 @@ module riscv_id_stage
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.data_misaligned_i ( data_misaligned_i ),
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.data_load_event_i ( data_load_event_ex_o ),
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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// ALU
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.mult_multicycle_i ( mult_multicycle_i ),
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`endif // MUL_SUPPORT
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// jump/branch control
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.branch_taken_ex_i ( branch_taken_ex ),
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@ -1034,6 +1066,8 @@ module riscv_id_stage
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imm_vec_ext_ex_o <= '0;
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alu_vec_mode_ex_o <= '0;
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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mult_operator_ex_o <= '0;
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mult_operand_a_ex_o <= '0;
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mult_operand_b_ex_o <= '0;
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@ -1047,6 +1081,7 @@ module riscv_id_stage
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mult_dot_op_b_ex_o <= '0;
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mult_dot_op_c_ex_o <= '0;
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mult_dot_signed_ex_o <= '0;
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`endif // MUL_SUPPORT
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regfile_waddr_ex_o <= 5'b0;
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regfile_we_ex_o <= 1'b0;
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@ -1091,15 +1126,24 @@ module riscv_id_stage
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data_misaligned_ex_o <= 1'b1;
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end
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end else if (mult_multicycle_i) begin
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end
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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else if (mult_multicycle_i) begin
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mult_operand_c_ex_o <= alu_operand_c;
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end
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`endif // MUL_SUPPORT
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else begin
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// normal pipeline unstall case
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if (id_valid_o)
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begin // unstall the whole pipeline
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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if (~mult_en)
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`else
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if (1'b1)
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`endif // MUL_SUPPORT
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begin // only change those registers when we actually need to
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alu_operator_ex_o <= alu_operator;
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alu_operand_a_ex_o <= alu_operand_a;
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@ -1111,6 +1155,8 @@ module riscv_id_stage
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alu_vec_mode_ex_o <= alu_vec_mode;
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end
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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mult_en_ex_o <= mult_en;
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if (mult_int_en) begin // when we are multiplying we don't need the ALU
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mult_operator_ex_o <= mult_operator;
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@ -1128,6 +1174,7 @@ module riscv_id_stage
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mult_dot_op_b_ex_o <= alu_operand_b;
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mult_dot_op_c_ex_o <= alu_operand_c;
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end
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`endif // MUL_SUPPORT
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regfile_we_ex_o <= regfile_we_id;
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if (regfile_we_id) begin
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