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Rework register file write data mux

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This commit is contained in:
Pirmin Vogel 2019-07-02 16:52:21 +01:00
parent 9e46bc50d5
commit 7924431144
4 changed files with 38 additions and 36 deletions
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6
rtl/ibex_core.sv
View file

@ -782,9 +782,9 @@ module ibex_core #(
.lsu_value_i ( data_wdata_ex ),
.ex_reg_addr_i ( id_stage_i.regfile_waddr_mux ),
.ex_reg_we_i ( id_stage_i.regfile_we_mux ),
.ex_reg_wdata_i ( id_stage_i.regfile_wdata_mux ),
.ex_reg_addr_i ( id_stage_i.regfile_waddr_id ),
.ex_reg_we_i ( id_stage_i.regfile_we ),
.ex_reg_wdata_i ( id_stage_i.regfile_wdata_id ),
.data_valid_lsu_i ( data_valid_lsu ),
.ex_data_addr_i ( data_addr_o ),
.ex_data_req_i ( data_req_o ),

10
rtl/ibex_decoder.sv
View file

@ -60,6 +60,7 @@ module ibex_decoder #(
output logic [1:0] multdiv_signed_mode_o,
// register file related signals
output ibex_defines::rf_wd_sel_e regfile_wdata_sel_o, // RF write data selection
output logic regfile_we_o, // write enable for regfile
// CSR manipulation
@ -107,6 +108,7 @@ module ibex_decoder #(
multdiv_operator_o = MD_OP_MULL;
multdiv_signed_mode_o = 2'b00;
regfile_wdata_sel_o = RF_WD_EX;
regfile_we_o = 1'b0;
csr_access_o = 1'b0;
@ -229,9 +231,10 @@ module ibex_decoder #(
end
OPCODE_LOAD: begin
data_req_o = 1'b1;
regfile_we_o = 1'b1;
data_type_o = 2'b00;
data_req_o = 1'b1;
regfile_wdata_sel_o = RF_WD_LSU;
regfile_we_o = 1'b1;
data_type_o = 2'b00;
// offset from immediate
alu_operator_o = ALU_ADD;
@ -463,6 +466,7 @@ module ibex_decoder #(
end else begin
// instruction to read/modify CSR
csr_access_o = 1'b1;
regfile_wdata_sel_o = RF_WD_CSR;
regfile_we_o = 1'b1;
alu_op_b_mux_sel_o = OP_B_IMM;
imm_a_mux_sel_o = IMM_A_Z;

6
rtl/ibex_defines.sv
View file

@ -153,6 +153,12 @@ typedef enum logic [2:0] {
IMM_B_INCR_ADDR
} imm_b_sel_e;
// Regfile write data selection
typedef enum logic [1:0] {
RF_WD_LSU,
RF_WD_EX,
RF_WD_CSR
} rf_wd_sel_e;
//////////////
// IF stage //

52
rtl/ibex_id_stage.sv
View file

@ -77,7 +77,7 @@ module ibex_id_stage #(
// Stalls
input logic ex_valid_i, // EX stage has valid output
input logic lsu_valid_i, // LSU has valid output, or is done
output logic id_valid_o, // ID stage is done
output logic id_valid_o, // ID stage is done
// ALU
output ibex_defines::alu_op_e alu_operator_ex_o,
@ -179,11 +179,6 @@ module ibex_id_stage #(
logic stall_branch;
logic stall_jump;
logic regfile_we;
typedef enum logic {RF_LSU, RF_EX} select_e;
select_e select_data_rf;
// Immediate decoding and sign extension
logic [31:0] imm_i_type;
logic [31:0] imm_s_type;
@ -204,11 +199,15 @@ module ibex_id_stage #(
logic [4:0] regfile_addr_ra_id;
logic [4:0] regfile_addr_rb_id;
logic [4:0] regfile_alu_waddr_id;
logic [4:0] regfile_waddr_id;
logic regfile_we_id, regfile_we_dec;
logic [31:0] regfile_data_ra_id;
logic [31:0] regfile_data_rb_id;
logic [31:0] regfile_wdata_id;
rf_wd_sel_e regfile_wdata_sel;
logic regfile_we;
// ALU Control
alu_op_e alu_operator;
@ -265,12 +264,12 @@ module ibex_id_stage #(
///////////////////////////
// Destination registers //
///////////////////////////
assign regfile_alu_waddr_id = instr[`REG_D];
assign regfile_waddr_id = instr[`REG_D];
//if (RV32E)
// assign illegal_reg_rv32e = (regfile_addr_ra_id[4] |
// regfile_addr_rb_id[4] |
// regfile_alu_waddr_id[4]);
// regfile_waddr_id[4]);
//else
assign illegal_reg_rv32e = 1'b0;
@ -335,22 +334,14 @@ module ibex_id_stage #(
// Registers //
///////////////
logic [31:0] regfile_wdata_mux;
logic regfile_we_mux;
logic [4:0] regfile_waddr_mux;
//TODO: add assertion
// Register File mux
always_comb begin
regfile_we_mux = regfile_we;
regfile_waddr_mux = regfile_alu_waddr_id;
if (select_data_rf == RF_LSU) begin
regfile_wdata_mux = regfile_wdata_lsu_i;
end else if (csr_access) begin
regfile_wdata_mux = csr_rdata_i;
end else begin
regfile_wdata_mux = regfile_wdata_ex_i;
end
// Register file write data mux
always_comb begin : regfile_wdata_mux
unique case (regfile_wdata_sel)
RF_WD_EX: regfile_wdata_id = regfile_wdata_ex_i;
RF_WD_LSU: regfile_wdata_id = regfile_wdata_lsu_i;
RF_WD_CSR: regfile_wdata_id = csr_rdata_i;
default: regfile_wdata_id = regfile_wdata_ex_i;
endcase;
end
ibex_register_file #( .RV32E ( RV32E ) ) registers_i (
@ -366,9 +357,9 @@ module ibex_id_stage #(
.raddr_b_i ( regfile_addr_rb_id ),
.rdata_b_o ( regfile_data_rb_id ),
// write port
.waddr_a_i ( regfile_waddr_mux ),
.wdata_a_i ( regfile_wdata_mux ),
.we_a_i ( regfile_we_mux )
.waddr_a_i ( regfile_waddr_id ),
.wdata_a_i ( regfile_wdata_id ),
.we_a_i ( regfile_we )
);
`ifdef RVFI
@ -376,8 +367,8 @@ module ibex_id_stage #(
assign rfvi_reg_rdata_ra_o = regfile_data_ra_id;
assign rfvi_reg_raddr_rb_o = regfile_addr_rb_id;
assign rfvi_reg_rdata_rb_o = regfile_data_rb_id;
assign rfvi_reg_waddr_rd_o = regfile_waddr_mux;
assign rfvi_reg_wdata_rd_o = regfile_wdata_mux;
assign rfvi_reg_waddr_rd_o = regfile_waddr_id;
assign rfvi_reg_wdata_rd_o = regfile_wdata_id;
assign rfvi_reg_we_o = regfile_we;
`endif
@ -414,6 +405,7 @@ module ibex_id_stage #(
.multdiv_signed_mode_o ( multdiv_signed_mode ),
// register file control signals
.regfile_wdata_sel_o ( regfile_wdata_sel ),
.regfile_we_o ( regfile_we_dec ),
// CSR control signals