Allow compiling the TB when the working directory isn't core_ibex

This makes things much easier for OpenTitan integration.

dv/uvm/core_ibex/scripts/compile-tb.py

@@ -9,7 +9,7 @@ import os
 import sys
 
 from ibex_cmd import get_compile_opts
-from scripts_lib import run_one, subst_vars
+from scripts_lib import THIS_DIR, run_one, subst_vars
 from sim_cmd import get_simulator_cmd
 
 
@@ -26,6 +26,13 @@ def main() -> int:
 
     args = parser.parse_args()
 
+    expected_env_vars = ['PRJ_DIR', 'LOWRISC_IP_DIR']
+    for var in expected_env_vars:
+        if os.getenv(var) is None:
+            raise RuntimeError(f'The environment variable {var!r} is not set.')
+
+    core_ibex = os.path.normpath(os.path.join(THIS_DIR, '..'))
+
     output_dir = os.path.join(args.output, 'rtl_sim')
     os.makedirs(output_dir, exist_ok=True)
 
@@ -39,6 +46,7 @@ def main() -> int:
     for pre_cmd in compile_cmds:
         cmd = subst_vars(pre_cmd,
                          {
+                             'core_ibex': core_ibex,
                              'out': output_dir,
                              'cmp_opts': get_compile_opts(args.ibex_config,
                                                           args.simulator)

dv/uvm/core_ibex/yaml/rtl_simulation.yaml

@@ -20,7 +20,7 @@
   env_var: IBEX_COSIM_ISS_ROOT,IBEX_ROOT
   compile:
     cmd:
-      - "vcs -f ibex_dv.f  -full64
+      - "vcs -f <core_ibex>/ibex_dv.f  -full64
          -l <out>/compile.log
          -sverilog -ntb_opts uvm-1.2
          +define+UVM
@@ -44,7 +44,7 @@
     wave_opts: >
       -debug_access+all -ucli -do vcs.tcl
     cosim_opts: >
-      -f ibex_dv_cosim_dpi.f
+      -f <core_ibex>/ibex_dv_cosim_dpi.f
       +define+INC_IBEX_COSIM
       -LDFLAGS '-L<IBEX_COSIM_ISS_ROOT>/lib/'
       -CFLAGS '-I<IBEX_COSIM_ISS_ROOT>/include'
@@ -74,7 +74,7 @@
     cmd:
       - "vmap mtiUvm $QUESTA_HOME/questasim/uvm-1.2"
       - "vlog -64
-              -f ibex_dv.f
+              -f <core_ibex>/ibex_dv.f
               -sv
               -mfcu -cuname design_cuname
               +define+UVM_REGEX_NO_DPI
@@ -101,7 +101,7 @@
                 +define+UVM
                 +define+DSIM
                 +acc+rwb
-                -f ibex_dv.f
+                -f <core_ibex>/ibex_dv.f
                 -l <out>/dsim/compile.log
                 -suppress EnumMustBePositive"
   sim:
@@ -119,7 +119,7 @@
         <cmp_opts>
         -uvmver 1.2
         +define+UVM
-        -f ibex_dv.f"
+        -f <core_ibex>/ibex_dv.f"
   sim:
     cmd: >
       vsim -c <sim_opts> <cov_opts> -sv_seed <seed> -lib <out>/work +UVM_TESTNAME=<rtl_test> +UVM_VERBOSITY=UVM_LOW +bin=<binary> +ibex_tracer_file_base="<sim_dir>/trace_core" -l <sim_dir>/sim.log -do "run -all; endsim; quit -force"
@@ -129,7 +129,7 @@
 - tool: qrun
   compile:
     cmd:
-      - "qrun -f ibex_dv.f -uvmhome uvm-1.2
+      - "qrun -f <core_ibex>/ibex_dv.f -uvmhome uvm-1.2
               +define+UVM
               -svinputport=net
               -access=rw+/. -optimize
@@ -151,7 +151,7 @@
     cmd:
       - "xrun -64bit
               -q
-              -f ibex_dv.f
+              -f <core_ibex>/ibex_dv.f
               -sv
               -licqueue
               -uvm