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[dv,fcov] Fix cp_mem_raw_hz implementation

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This commit fixes how we catch an instruction at WB stage. Before this fix
we were effectively checking opcode of decoded instruction instead.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit is contained in:
Canberk Topal 2022-07-25 09:41:33 +01:00 • committed by Canberk Topal
parent 6518cb6db6
commit 7bae3b7ba3
1 changed files with 1 additions and 1 deletions
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dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
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@ -338,7 +338,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
// If we have LOAD at ID/EX stage and STORE at WB stage, compare the calculated address for LOAD
// and the saved STORE address. If they are matching we would have RAW hazard.
assign raw_hz = id_stage_i.instr_type_wb_o == WB_INSTR_STORE &&
assign raw_hz = wb_stage_i.outstanding_store_wb_o &&
id_instr_category == InstrCategoryLoad &&
prev_store_addr == curr_data_addr;