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[dv] Improve riscv_core_setting.sv template

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This now takes into account more configuration options allow DV to run
successfully across more configs.
This commit is contained in:
Greg Chadwick 2022-08-23 17:37:40 +01:00 • committed by Greg Chadwick
parent 3d76300686
commit 7c37648b06
1 changed files with 24 additions and 28 deletions
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52
dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv
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@ -52,8 +52,13 @@ riscv_instr_name_t unsupported_instr[] = {};
bit support_unaligned_load_store = 1'b1;
// ISA supported by the processor
riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C,
RV32ZBA, RV32ZBB, RV32ZBC, RV32ZBS, RV32B};
// TODO: Determine how Ibex RV32B types map to RISCV-DV ISA names
riscv_instr_group_t supported_isa[$] = {RV32I, RV32M, RV32C
% if ibex_config['RV32B'] == 'ibex_pkg::RV32BNone':
};
% else:
,RV32ZBA, RV32ZBB, RV32ZBC, RV32ZBS, RV32B};
% endif
// Interrupt mode support
mtvec_mode_t supported_interrupt_mode[$] = {VECTORED};
@ -124,30 +129,12 @@ const privileged_reg_t implemented_csr[] = {
MINSTRET, // Machine instructions retired counter (lower 32 bits)
MINSTRETH, // Machine instructions retired counter (upper 32 bits)
MCOUNTINHIBIT, // Machine counter inhibit register
MHPMEVENT3, // Machine performance monitoring event selector
MHPMEVENT4, // Machine performance monitoring event selector
MHPMEVENT5, // Machine performance monitoring event selector
MHPMEVENT6, // Machine performance monitoring event selector
MHPMEVENT7, // Machine performance monitoring event selector
MHPMEVENT8, // Machine performance monitoring event selector
MHPMEVENT9, // Machine performance monitoring event selector
MHPMEVENT10, // Machine performance monitoring event selector
MHPMCOUNTER3, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER4, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER5, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER6, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER7, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER8, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER9, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER10, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER3H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER4H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER5H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER6H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER7H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER8H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER9H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER10H, // Machine performance monitoring counter (upper 32 bits)
% for pcount_num in range(ibex_config['MHPMCounterNum']):
MHPMEVENT${pcount_num + 3}, // Machine performance monitoring event selector
MHPMCOUNTER${pcount_num + 3}, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER${pcount_num + 3}H, // Machine performance monitoring counter (lower 32 bits)
% endfor
% if ibex_config['PMPEnable']:
PMPCFG0, // PMP configuration register
PMPCFG1, // PMP configuration register
PMPCFG2, // PMP configuration register
@ -168,23 +155,32 @@ const privileged_reg_t implemented_csr[] = {
PMPADDR13, // PMP address register
PMPADDR14, // PMP address register
PMPADDR15, // PMP address register
% endif
DCSR, // Debug control and status register
DPC, // Debug PC
DSCRATCH0, // Debug scratch register 0
DSCRATCH1, // Debug scratch register 1
TSELECT, // Trigger select register
DSCRATCH1, // Debug scratch register 1
% if ibex_config['DbgTriggerEn']:
TSELECT, // Trigger select register
TDATA1, // Trigger data register 1
TDATA2, // Trigger data register 2
TDATA3, // Trigger data register 3
% endif
MCONTEXT, // Machine context register
SCONTEXT // Supervisor context register
};
// TODO: Co-simulation fix required so cpuctrl behaves correctly in co-sim for all ibex configs. For
// now we only test it when all fields are available.
% if ibex_config['SecureIbex'] and ibex_config['ICache']:
// Implementation-specific custom CSRs
const bit [11:0] custom_csr[] = {
12'h7C0, // cpuctrl - CPU control register
12'h7C1 // secureseed - Security feature random seed register
};
% else:
const bit [11:0] custom_csr[] = {};
% endif
// --------------------------------------------------------------------------
// Supported interrupt/exception setting, used for functional coverage