mirror of
https://github.com/lowRISC/ibex.git
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Avoid unneccessary rebuilding in dv/uvm/core_ibex/Makefile
Before this patch, running the Makefile's default target deleted everything and then ran the whole flow. This sometimes does unnecessary work (if I've just changed the design, there's no need to rebuild and re-run the instruction generator). It also definitely won't work with Make's -j flag, since it depends on the targets being built in order. This patch keeps the same stages in the Makefile, but makes each stage generate a stamp file, adding dependencies between the stages. This way, you can make a small change to the design and re-run the simulation without having to generate the random inputs again. This doesn't make much difference if you're running lots of tests with no LSF (since VCS is very slow, its runtime for simulation completely dominates), but it can make a significant difference if you're debugging a single test, have made a change to the design and want to re-run. One significant change is that running 'make' doesn't automatically delete existing files any more. To make this possible (and useful!), we generate random data and test results in a directory keyed by the seed. For example make SEED=123 will generate results in out/seed-123/regr.log (rather than out/regr.log as before). To make sure we rebuild things properly if you change something like the number of iterations or the tests to run, we dump some variables describing the mode in which we were running. If these don't match the nnext time around, we'll rebuild stuff if necessary. Advanced (or hurried) users of the existing Makefile might have done things like change the design and then run make SEED=123 compile rtl_sim Now, the rtl_sim target depends on its logical dependencies. On the plus side, this means that you won't accidentally simulate out-of-date code. On the minus side, cunning tricks to avoid having to re-run stuff after touching a design file won't work. (If you're feeling really determined to do something like that, it's still possible with make -t). The seed-specific stamp files and dumped Make variables go into $(OUT-SEED)/.metadata directory, rather than $(OUT-SEED)/instr_gen or $(OUT-SEED)/rtl_sim. This is because of a review comment (to avoid extra clutter in the output directories).
This commit is contained in:
Rupert Swarbrick
Rupert Swarbrick
parent
91d7721fa9
commit
7df14341ef
1 changed files with 257 additions and 49 deletions
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@ -5,7 +5,22 @@
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DV_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
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GEN_DIR := $(realpath ${DV_DIR}/../../../vendor/google_riscv-dv)
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TOOLCHAIN := ${RISCV_TOOLCHAIN}
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OUT := "${DV_DIR}/out"
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# Seed for instruction generator and RTL simulation
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#
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# By default, SEED is set to a different value on each run by picking a random
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# value in the Makefile. For overnight testing, a sensible seed might be
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# something like the output of "date +%y%m%d". For regression testing, you'll
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# need to make sure that a the seed for a failed test "sticks" (so we don't
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# start passing again without fixing the bug).
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SEED := $(shell echo $$RANDOM)
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# This is the top-level output directory. Everything we generate goes in
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# here. Most generated stuff actually goes in $(OUT)/seed-$(SEED), which allows
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# us to run multiple times without deleting existing results.
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OUT := ${DV_DIR}/out
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OUT-SEED := $(OUT)/seed-$(SEED)
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# Run time options for the instruction generator
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GEN_OPTS :=
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# Compile time options for ibex RTL simulation
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@ -26,9 +41,7 @@ ISS_OPTS :=
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ISA := rv32imc
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# Test name (default: full regression)
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TEST := all
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# Seed for instruction generator and RTL simulation
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TESTLIST := ${DV_DIR}/riscv_dv_extension/testlist.yaml
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SEED := -1
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# Verbose logging
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VERBOSE :=
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# Number of iterations for each test, assign a non-zero value to override the
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@ -68,29 +81,28 @@ endif
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SHELL=/bin/bash
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export PRJ_DIR:= $(realpath ${DV_DIR}/../../../../)
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export PRJ_DIR:= $(realpath ${DV_DIR}/../../../..)
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.PHONY: rtl_sim clean gcc_compile iss_sim
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all: sim
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all: clean gen gcc_compile iss_sim compile rtl_sim post_compare
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instr: iss_sim
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instr: gen gcc_compile iss_sim
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sim: compile rtl_sim post_compare
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sim: post_compare
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.PHONY: clean
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clean:
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rm -rf ${OUT}
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# Common options for all targets
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COMMON_OPTS:=--seed=${SEED} \
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COMMON_OPTS := $(if $(call equal,$(VERBOSE),1),--verbose,)
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# Options for all targets that depend on the tests we're running.
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TEST_OPTS := $(COMMON_OPTS) \
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--seed=${SEED} \
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--test"=${TEST}" \
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--testlist=${TESTLIST} \
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--iterations=${ITERATIONS}
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ifeq ($(VERBOSE), 1)
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COMMON_OPTS+=--verbose
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endif
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# Options used for privileged CSR test generation
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CSR_OPTS=--csr_yaml=${CSR_FILE} \
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--isa="${ISA}" \
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@ -100,45 +112,208 @@ RISCV_DV_OPTS=--custom_target=${DV_DIR}/riscv_dv_extension \
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--isa="${ISA}" \
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--mabi=ilp32 \
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# To avoid cluttering the output directory with stamp files, we place them in
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# $(metadata).
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metadata := $(OUT-SEED)/.metadata
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# This is a list of directories that are automatically generated by some
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# targets. To ensure the directory has been built, add a order-only dependency
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# (with the pipe symbol before it) on the directory name and add the directory
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# to this list.
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gen-dirs := $(OUT) $(OUT-SEED) $(metadata) $(OUT)/rtl_sim
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$(gen-dirs): %:
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mkdir -p $@
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###############################################################################
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# Utility functions.
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#
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# If VS is a list of variable names, P is a path and X is a string, then $(call
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# dump-vars,P,X,VS) will expand to a list of 'file' commands that write each
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# variable to P in Makefile syntax, but with "last-X-" prepended. At the start
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# of the file, we also define last-X-vars-loaded to 1. You can use this to
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# check whether there was a dump file at all.
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#
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# Note that this doesn't work by expanding to a command. Instead, *evaluating*
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# dump-vars causes the variables to be dumped.
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dump-var = $(file >>$(1),last-$(2)-$(3) := $($(3)))
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dump-vars = $(file >$(1),last-$(2)-vars-loaded := .) \
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$(foreach name,$(3),$(call dump-var,$(1),$(2),$(name)))
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# equal checks whether two strings are equal, evaluating to '.' if they are and
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# '' otherwise.
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both-empty = $(if $(1),,$(if $(2),,.))
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find-find = $(if $(and $(findstring $(1),$(2)),$(findstring $(2),$(1))),.,)
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equal = $(or $(call both-empty,$(1),$(2)),$(call find-find,$(1),$(2)))
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# var-differs is used to check whether a variable has changed since it was
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# dumped. If it has changed, the function evaluates to '.' (with some
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# whitespace) and prints a message to the console; if not, it evaluates to ''.
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#
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# Call it as $(call var-differs,X,TGT,V).
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var-differs = \
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$(if $(call equal,$(strip $($(3))),$(strip $(last-$(1)-$(3)))),,\
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.$(info Repeating $(2) because variable $(3) has changed value.))
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# vars-differ is used to check whether several variables have the same value as
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# they had when they were dumped. If we haven't loaded the dumpfile, it
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# silently evaluates to '!'. Otherwise, if all the variables match, it
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# evaluates to '.'. If not, it evaluates to '.' and prints some messages to the
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# console explaining why a rebuild is happening.
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#
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# Call it as $(call vars-differ,X,TGT,VS).
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vars-differ-lst = $(foreach v,$(3),$(call var-differs,$(1),$(2),$(v)))
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vars-differ-sp = \
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$(if $(last-$(1)-vars-loaded),\
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$(if $(strip $(call vars-differ-lst,$(1),$(2),$(3))),.,),\
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!)
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vars-differ = $(strip $(call vars-differ-sp,$(1),$(2),$(3)))
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# A phony target which can be used to force recompilation.
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.PHONY: FORCE
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FORCE:
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# vars-prereq is empty if every variable in VS matches the last run (loaded
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# with tag X), otherwise it is set to FORCE (which will force a recompile and
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# might print a message to the console explaining why we're rebuilding TGT).
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#
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# Call it as $(call vars-prereq,X,TGT,VS)
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vars-prereq = $(if $(call vars-differ,$(1),$(2),$(3)),FORCE,)
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###############################################################################
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# Generate random instructions
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.SILENT gen:
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mkdir -p ${OUT}
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python3 ${GEN_DIR}/run.py \
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--output=${OUT}/instr_gen ${GEN_OPTS} \
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#
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# This depends on the vendored in code in $(GEN_DIR). It also depends on the
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# values of some variables (we want to regenerate things if, for example, the
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# simulator changes). Since we're writing out to $(OUT-SEED), we don't have to
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# depend on the value of SEED. However, we do have to make sure that the
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# variables whose names are listed in $(gen-var-deps) haven't changed.
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#
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# To do this variable tracking, we dump each of the variables to a Makefile
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# fragment and try to load it up the next time around.
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gen-var-deps := GEN_OPTS SIMULATOR RISCV_DV_OPTS CSR_OPTS \
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SIGNATURE_ADDR PMP_REGIONS PMP_GRANULARITY TEST_OPTS
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# Load up the generation stage's saved variable values. If this fails, that's
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# no problem: we'll assume that the previous run either doesn't exist or
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# something went wrong.
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-include $(metadata)/gen-vars.mk
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# gen-vars-prereq is empty if every variable in gen-var-deps matches the last run,
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# otherwise it is set to FORCE (which will force a recompile). Note that we
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# define it with '=', not ':=', so we don't evaluate it if we're not trying to
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# run the gen target.
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gen-vars-prereq = \
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$(call vars-prereq,gen,building instruction generator,$(gen-var-deps))
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# A variable containing a file list for the riscv-dv vendored-in module.
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# Depending on these files gives a safe over-approximation that will ensure we
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# rebuild things if that module changes.
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#
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# Note that this is defined with ":=". As a result, we'll always run the find
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# command exactly once. Wasteful if we're trying to make clean, but much better
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# than running it for every target otherwise.
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risc-dv-files := $(shell find $(GEN_DIR) -type f)
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# This actually runs the instruction generator. Note that the rule depends on
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# the (phony) FORCE target if any variables have changed. If the rule actually
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# runs, it starts by deleting any existing contents of $(OUT-SEED)/instr_gen.
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$(metadata)/instr_gen.gen.stamp: \
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$(gen-vars-prereq) $(risc-dv-files) | $(metadata)
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@rm -rf $(OUT-SEED)/instr_gen
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@python3 ${GEN_DIR}/run.py \
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--output=$(OUT-SEED)/instr_gen ${GEN_OPTS} \
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--steps=gen \
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--gen_timeout=${TIMEOUT} \
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--lsf_cmd="${LSF_CMD}" \
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--simulator="${SIMULATOR}" \
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${RISCV_DV_OPTS} \
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${COMMON_OPTS} \
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${TEST_OPTS} \
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${CSR_OPTS} \
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--sim_opts="+uvm_set_inst_override=riscv_asm_program_gen,ibex_asm_program_gen,"uvm_test_top.asm_gen" \
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+signature_addr=${SIGNATURE_ADDR} +pmp_num_regions=${PMP_REGIONS} \
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+pmp_granularity=${PMP_GRANULARITY}";
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+pmp_granularity=${PMP_GRANULARITY}"
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$(call dump-vars,$(metadata)/gen-vars.mk,gen,$(gen-var-deps))
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@touch $@
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# Compile the generated assmebly programs to ELF/BIN
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gcc_compile:
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python3 ${GEN_DIR}/run.py \
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--o=${OUT}/instr_gen ${GEN_OPTS} \
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.PHONY: gen
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gen: $(metadata)/instr_gen.gen.stamp
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###############################################################################
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# Compile the generated assembly programs
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#
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# We don't explicitly track dependencies on the RISCV toolchain, so this
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# doesn't depend on anything more than the instr_gen stage did.
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$(metadata)/instr_gen.compile.stamp: $(metadata)/instr_gen.gen.stamp
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@python3 ${GEN_DIR}/run.py \
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--o=$(OUT-SEED)/instr_gen ${GEN_OPTS} \
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--steps=gcc_compile \
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${COMMON_OPTS} \
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${TEST_OPTS} \
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--gcc_opts=-mno-strict-align \
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${RISCV_DV_OPTS} \
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${RISCV_DV_OPTS} && \
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touch $@
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# ISS simulation
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iss_sim:
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python3 ${GEN_DIR}/run.py \
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--o=${OUT}/instr_gen ${GEN_OPTS} \
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.PHONY: gcc_compile
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gcc_compile: $(metadata)/instr_gen.compile.stamp
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###############################################################################
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# Run the instruction set simulator
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#
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# This (obviously) depends on having compiled the generated programs, so we
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# don't have to worry about variables that affect the 'gen' stage. However, the
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# ISS and ISS_OPTS variables do affect the output, so we need to dump them. See
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# the 'gen' stage for more verbose explanations of how this works.
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iss-var-deps := ISS ISS_OPTS
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-include $(metadata)/iss-vars.mk
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iss-vars-prereq = $(call vars-prereq,iss,running ISS,$(iss-var-deps))
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$(metadata)/instr_gen.iss.stamp: \
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$(iss-vars-prereq) $(metadata)/instr_gen.compile.stamp
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@python3 ${GEN_DIR}/run.py \
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--o=$(OUT-SEED)/instr_gen ${GEN_OPTS} \
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--steps=iss_sim \
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${COMMON_OPTS} \
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${TEST_OPTS} \
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--iss="${ISS}" \
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--iss_opts="${ISS_OPTS}" \
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${RISCV_DV_OPTS} \
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${RISCV_DV_OPTS}
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$(call dump-vars,$(metadata)/iss-vars.mk,iss,$(iss-var-deps))
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@touch $@
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.PHONY: iss_sim
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iss_sim: $(metadata)/instr_gen.iss.stamp
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###############################################################################
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# Compile ibex core TB
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compile:
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mkdir -p ${OUT}/rtl_sim;
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python3 ./sim.py \
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#
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# Note that (unlike everything else) this doesn't depend on the seed: the DUT
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# doesn't depend on which test we're running!
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#
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# It does, however, depend on various variables. These are listed in
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# compile-var-deps. See the 'gen' stage for more verbose explanations of how
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# the variable dumping works.
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#
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# The compiled ibex testbench (obviously!) also depends on the design and the
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# DV code. The clever way of doing this would be to look at a dependency
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# listing generated by the simulator as a side-effect of doing the compile (a
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# bit like using the -M flags with a C compiler). Unfortunately, that doesn't
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# look like it's particularly easy, so we'll just depend on every .v, .sv or
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# .svh file in the dv or rtl directories. Note that this variable is set with
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# '=', rather than ':='. This means that we don't bother running the find
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# commands unless we need the compiled testbench.
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all-verilog = \
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$(shell find ../../../rtl -name '*.v' -o -name '*.sv' -o -name '*.svh') \
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$(shell find ../.. -name '*.v' -o -name '*.sv' -o -name '*.svh')
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compile-var-deps := COMMON_OPTS SIMULATOR COV WAVES COMPILE_OPTS
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-include $(OUT)/rtl_sim/.compile-vars.mk
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compile-vars-prereq = $(call vars-prereq,comp,compiling TB,$(compile-var-deps))
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$(call dump-vars-match,$(compile-var-deps),comp)
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$(OUT)/rtl_sim/.compile.stamp: \
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$(compile-vars-prereq) $(all-verilog) $(risc-dv-files) | $(OUT)/rtl_sim
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@python3 ./sim.py \
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--o=${OUT} \
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--riscv_dv_root=${GEN_DIR} \
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--steps=compile \
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@ -146,34 +321,67 @@ compile:
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--simulator="${SIMULATOR}" \
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--en_cov=${COV} \
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--en_wave=${WAVES} \
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--cmp_opts="${COMPILE_OPTS}" \
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--cmp_opts="${COMPILE_OPTS}"
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$(call dump-vars,$(OUT)/rtl_sim/.compile-vars.mk,comp,$(compile-var-deps))
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@touch $@
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# Run ibex RTL simulation with random instructions
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rtl_sim:
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mkdir -p ${OUT}/rtl_sim
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python3 ./sim.py \
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--o=${OUT} \
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.PHONY: compile
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compile: $(OUT)/rtl_sim/.compile.stamp
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###############################################################################
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# Run ibex RTL simulation with generated programs
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#
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# Because we compile a TB once rather than for each seed, we have to copy in
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# that directory before we start. We make this step (rather than actually
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# running the test) dependent on having the right variables. That way, we'll
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# correctly delete the sim directory and re-copy it if necessary.
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#
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# Note that the variables we depend on are gen-vars-prereq. We also depend on
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# COV and WAVES, but these dependencies will come for free from the dependency
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# on the compiled TB.
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$(metadata)/rtl_sim.compile.stamp: \
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$(gen-vars-prereq) $(risc-dv-files) $(OUT)/rtl_sim/.compile.stamp
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rm -rf $(OUT-SEED)/rtl_sim
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cp -r $(OUT)/rtl_sim $(OUT-SEED)
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@touch $@
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# This rule actually runs the simulation. It depends on the copied-in testbench
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# and also on us having already compiled the test programs.
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$(metadata)/rtl_sim.run.stamp: \
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$(metadata)/rtl_sim.compile.stamp $(metadata)/instr_gen.compile.stamp
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@python3 ./sim.py \
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--o=$(OUT-SEED) \
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--riscv_dv_root=${GEN_DIR} \
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--steps=sim \
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${COMMON_OPTS} \
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${TEST_OPTS} \
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--simulator="${SIMULATOR}" \
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--en_cov ${COV} \
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--en_wave ${WAVES} \
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--lsf_cmd="${LSF_CMD}" \
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--sim_opts="+signature_addr=${SIGNATURE_ADDR}" \
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${SIM_OPTS}
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@touch $@
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# Compare the regression result between ISS and RTL sim
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post_compare:
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rm -rf ${OUT}/regr.log
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python3 ./sim.py \
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--o=${OUT} \
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.PHONY: rtl_sim
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rtl_sim: $(metadata)/rtl_sim.run.stamp
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###############################################################################
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# Compare ISS and RTL sim results
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$(OUT-SEED)/regr.log: \
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$(metadata)/instr_gen.iss.stamp \
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$(metadata)/rtl_sim.run.stamp
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@rm -f $@
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@python3 ./sim.py \
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--o=$(OUT-SEED) \
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--steps=compare \
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${COMMON_OPTS} \
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${TEST_OPTS} \
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--simulator="${SIMULATOR}" \
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--iss="${ISS}"
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.PHONY: post_compare
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post_compare: $(OUT-SEED)/regr.log
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###############################################################################
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# Generate functional coverage
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fcov:
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python3 ${GEN_DIR}/cov.py \
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||||
|
|
@ -190,5 +398,5 @@ cov_vcs:
|
|||
cov_ius:
|
||||
if [ ! -d "${OUT}/rtl_sim/cov_work/scope/merged_cov" ]; \
|
||||
then imc -execcmd "merge -out ${OUT}/rtl_sim/cov_work/scope/merged_cov ${OUT}/rtl_sim/cov_work/scope/test_*"; \
|
||||
fi
|
||||
fi
|
||||
imc -load ${OUT}/rtl_sim/cov_work/scope/merged_cov &
|
||||
|
|
|
|||
Loading…
Add table
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Reference in a new issue