Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
be1359d27d0e826e28e6611f318c286253cd05f1

* [secded_gen] Enhance inverted ECC code (Michael Schaffner)
* [rtl] Add CRC32 primitive (Greg Chadwick)
* [syn/cdc] Minor flow fixes in CDC and syn scripts (Michael
  Schaffner)
* [dv] Minor update on mem_model (Weicai Yang)
* [dv/prim_alert] Clean up alert test (Cindy Chen)
* [bazel] Build verilator with bazel (Chris Frantz)
* [cdc] Add support for initial CDC flow with open-source views
  (Michael Schaffner)
* [lc_ctrl/dv,dv_lib,dv_utils,csr_utils] Added JTAG CSR Infrastructure
  (Nigel Scales)
* [prim] Add a lint waiver for dv-only code / ifdefs (Timothy Chen)

Signed-off-by: Michael Schaffner <msf@google.com>
This commit is contained in:
Michael Schaffner 2021-12-07 19:44:54 -08:00 committed by Greg Chadwick
parent c78acac8cc
commit 804c538db2
115 changed files with 1870 additions and 645 deletions

View file

@ -714,6 +714,58 @@ package csr_utils_pkg;
return null;
endfunction
// Clone a UVM address map
function automatic uvm_reg_map clone_reg_map(
string name, uvm_reg_map map, uvm_reg_addr_t base_addr = 0, int n_bytes = 4,
uvm_endianness_e endian = UVM_LITTLE_ENDIAN, bit byte_addressing = 1);
uvm_reg_map clone;
uvm_reg_map submaps[$];
uvm_reg regs[$];
uvm_reg_block blk;
uvm_mem mems[$];
// Clone the map
blk = map.get_parent();
clone = blk.create_map(
.name(name),
.base_addr(base_addr),
.n_bytes(n_bytes),
.endian(endian),
.byte_addressing(byte_addressing)
);
// Clone the submaps by calling this function recursively
map.get_submaps(submaps);
if (submaps.size()) `dv_warning("clone_reg_map: submaps are not yet tested", "DV_UTILS_PKG")
while (submaps.size()) begin
uvm_reg_map submap, submap_clone;
submap = submaps.pop_front();
submap_clone = clone_reg_map(.name(name), .map(submap), .base_addr(submap.get_base_addr()),
.n_bytes(submap.get_n_bytes()), .endian(endian));
clone.add_submap(.child_map(submap_clone), .offset(clone.get_submap_offset(submap)));
end
// Clone the registers
map.get_registers(regs, UVM_NO_HIER);
while (regs.size()) begin
uvm_reg rg;
rg = regs.pop_front();
clone.add_reg(.rg(rg), .offset(rg.get_offset(map)), .rights(rg.get_rights(map)), .unmapped(0),
.frontdoor(null));
end
// Clone the memories
map.get_memories(mems, UVM_NO_HIER);
while (mems.size()) begin
uvm_mem mem;
mem = mems.pop_front();
clone.add_mem(.mem(mem), .offset(mem.get_offset(0, map)), .rights(mem.get_rights(map)),
.unmapped(0), .frontdoor(null));
end
return clone;
endfunction
// sources
`include "csr_seq_lib.sv"

View file

@ -16,13 +16,22 @@ class dv_base_test #(type CFG_T = dv_base_env_cfg,
uint drain_time_ns = 2_000; // 2us
bit poll_for_stop = 1'b0;
uint poll_for_stop_interval_ns = 1000;
bit print_topology = 1'b0;
`uvm_component_new
virtual function void build_phase(uvm_phase phase);
dv_report_server m_dv_report_server = new();
dv_report_server m_dv_report_server = new();
dv_report_catcher m_report_catcher;
uvm_report_server::set_server(m_dv_report_server);
// Message catcher/demoter
`uvm_create_obj(dv_report_catcher, m_report_catcher)
// Add demoted messages - we need to do this here to catch build warnings
add_message_demotes(m_report_catcher);
// Register catcher
uvm_report_cb::add(null, m_report_catcher);
super.build_phase(phase);
env = ENV_T::type_id::create("env", this);
@ -44,6 +53,10 @@ class dv_base_test #(type CFG_T = dv_base_env_cfg,
// Enable reduced runtime test.
void'($value$plusargs("smoke_test=%0b", cfg.smoke_test));
// Enable print_topology
void'($value$plusargs("print_topology=%0b", print_topology));
uvm_top.enable_print_topology = print_topology;
endfunction : build_phase
virtual function void end_of_elaboration_phase(uvm_phase phase);
@ -67,6 +80,10 @@ class dv_base_test #(type CFG_T = dv_base_env_cfg,
// TODO: add hook for end of test checking.
endtask : run_phase
// Add message demotes here - hook to use by extended tests
virtual function void add_message_demotes(dv_report_catcher catcher);
endfunction
virtual task run_seq(string test_seq_s, uvm_phase phase);
uvm_sequence test_seq = create_seq_by_name(test_seq_s);

View file

@ -0,0 +1,46 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// Report catcher/demoter
class dv_report_catcher extends uvm_report_catcher;
// Stores a new severity indexed by the ID and
// the regular expression to match the message
protected uvm_severity m_changed_sev[string][string];
`uvm_object_utils(dv_report_catcher)
`uvm_object_new
// Called for all report messages - defined in uvm_report_catcher
virtual function action_e catch();
string id = get_id();
if (m_changed_sev.exists(id)) begin
string report_msg = get_message();
foreach (m_changed_sev[id][msg]) begin
if (uvm_re_match(msg, report_msg)) begin
set_severity(m_changed_sev[id][msg]);
end
end
end
return THROW;
endfunction
// Change severity of a message with ID == id and message text
// matching msg which is treated as a regular expression
virtual function void add_change_sev(string id, string msg, uvm_severity sev);
m_changed_sev[id][msg] = sev;
endfunction
// Remove a change entry
// If msg == "" then remove all changes for a given id
virtual function void remove_change_sev(string id, string msg = "");
if (m_changed_sev.exists(id))
if (msg == "") begin
// Delete all with id if message is blank
m_changed_sev.delete(id);
end else if (m_changed_sev[id].exists(msg)) begin
m_changed_sev[id].delete(msg);
end
endfunction
endclass

View file

@ -17,6 +17,7 @@ filesets:
- lowrisc:dv:dv_test_status
files:
- dv_utils_pkg.sv
- dv_report_catcher.sv: {is_include_file: true}
- dv_report_server.sv: {is_include_file: true}
- dv_vif_wrap.sv: {is_include_file: true}
file_type: systemVerilogSource

View file

@ -215,6 +215,7 @@ package dv_utils_pkg;
// sources
`ifdef UVM
`include "dv_report_catcher.sv"
`include "dv_report_server.sv"
`include "dv_vif_wrap.sv"
`endif

View file

@ -9,6 +9,7 @@ filesets:
files_dv:
depend:
- lowrisc:opentitan:bus_params_pkg
- lowrisc:dv:dv_macros
files:
- mem_model_pkg.sv
- mem_model.sv: {is_include_file: true}

View file

@ -3,8 +3,9 @@
// SPDX-License-Identifier: Apache-2.0
class mem_model #(int AddrWidth = bus_params_pkg::BUS_AW,
int DataWidth = bus_params_pkg::BUS_DW,
int MaskWidth = bus_params_pkg::BUS_DBW) extends uvm_object;
int DataWidth = bus_params_pkg::BUS_DW) extends uvm_object;
localparam int MaskWidth = DataWidth / 8;
typedef bit [AddrWidth-1:0] mem_addr_t;
typedef bit [DataWidth-1:0] mem_data_t;

View file

@ -7,6 +7,7 @@ package mem_model_pkg;
import uvm_pkg::*;
`include "uvm_macros.svh"
`include "dv_macros.svh"
`include "mem_model.sv"
endpackage