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Intermediate commit, trying out some things
This commit is contained in:
Sven Stucki
parent
8e26797549
commit
80ca650893
1 changed files with 247 additions and 132 deletions
379
if_stage.sv
379
if_stage.sv
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@ -24,8 +24,8 @@
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// comments //
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// Revision v0.3 - (December 1th 2014) Merged debug unit and added more //
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// exceptions //
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// Revision v0.4 - (July 30th 2015) Removed instr_core_interface, handling //
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// the cache interface in IF now //
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// Revision v0.4 - (July 30th 2015) Moved instr_core_interface into IF, //
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// handling compressed instructions with FSM //
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// //
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// //
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////////////////////////////////////////////////////////////////////////////////
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@ -90,18 +90,21 @@ module if_stage
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logic [31:0] exc_pc; // PC from exception
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enum logic [2:0] {IDLE, WAIT_BRANCH, FETCH_STALLED, FETCH_UNSTALLED, WAIT_IF_STALL} CS, NS;
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//enum logic [2:0] {IDLE, WAIT_BRANCH, FETCH_STALLED, FETCH_UNSTALLED, WAIT_IF_STALL} CS, NS;
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// PC generation FSM
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enum logic [0:0] {REGULAR, HANDLE_BRANCH} CS_PCGEN, NS_PCGEN;
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// instruction cache interface signals
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//enum logic [1:0] {IDLE, WAIT_GNT, WAIT_RVALID, WAIT_IF_STALL} CS_FETCH, NS_FETCH;
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logic sample_addr;
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logic [31:0] fetch_addr, fetch_addr_n;
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logic [31:0] fetch_data, fetch_data_n;
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logic [31:0] instr_addr_o_n;
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0) begin
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fetch_addr <= '0;
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end else begin
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if (sample_addr)
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fetch_addr <= fetch_addr_n;
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end
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end
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logic [31:0] last_fetch_addr;
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@ -110,23 +113,233 @@ module if_stage
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// instr_core_interface
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logic req_int;
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logic ack_int;
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logic [31:0] addr_int;
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logic [31:0] rdata_int;
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// local cache
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logic [31:0] data_tag;
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logic [1:0][31:0] data_arr;
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logic bypass_data_reg; // use data from instr_core_if, not from data_arr
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logic pc_if_offset, pc_if_offset_n;
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enum logic[3:0] {INVALID, VALID, FETCH, FETCH_NEXT, SERVE_OFFSET} fetch_fsm_cs, fetch_fsm_ns;
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0) begin
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fetch_fsm_cs <= INVALID;
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pc_if_offset <= '0;
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end else begin
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fetch_fsm_cs <= fetch_fsm_ns;
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pc_if_offset <= pc_if_offset_n;
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end
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end
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logic force_nop_int;
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logic handle_branch;
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logic do_fetch;
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logic [31:0] instr_rdata_int;
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assign instr_rdata_int = (force_nop_int == 1'b0)? rdata_int : {25'b0, `OPCODE_OPIMM};
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// increased PC calculation
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logic fetch_unaligned;
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logic fetch_hit;
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logic [1:0] is_compressed;
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assign compressed_instr = instr_rdata_int[1:0] != 2'b11;
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assign do_fetch = req_i;
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always_comb
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begin
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if (rdata_int[1:0] != 2'b11) begin
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// compressed instruction
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incr_pc = current_pc_if_o + 32'd2;
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if (pc_if_offset) begin
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incr_pc = fetch_addr + (is_compressed[1] ? 32'd2 : 32'd4);
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end else begin
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incr_pc = current_pc_if_o + 32'd4;
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incr_pc = fetch_addr + (is_compressed[0] ? 32'd2 : 32'd4);
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end
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end
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//assign incr_pc = current_pc_if_o + (instr_rdata_int[1:0] != 2'b11 ? 32'd2 : 32'd4);
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// store instr_core_if data in local cache
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0) begin
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data_tag <= '0;
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data_arr <= '0;
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end else begin
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if (ack_int) begin
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data_tag <= last_fetch_addr;
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data_arr[1] <= data_arr[0];
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data_arr[0] <= rdata_int;
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end
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end
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end
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// cache data output muxes
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always_comb
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begin
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if (bypass_data_reg) begin
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// bypass cache and get data directly from instr_core_if
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if (pc_if_offset)
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instr_rdata_int = {rdata_int[15:0], data_arr[0][31:16]};
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else
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instr_rdata_int = rdata_int;
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end else begin
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// serve data from cache
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if (pc_if_offset)
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instr_rdata_int = {data_arr[0][15:0], data_arr[1][31:16]};
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else
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instr_rdata_int = data_arr[0];
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end
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if (force_nop_int)
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instr_rdata_int = {25'b0, `OPCODE_OPIMM};
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end
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assign is_compressed[0] = instr_rdata_int[1:0] != 2'b11;
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assign is_compressed[1] = instr_rdata_int[17:16] != 2'b11;
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assign current_pc_if_o = pc_if_offset ? {fetch_addr[31:2], 2'b10} : fetch_addr;
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always_comb
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begin
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fetch_unaligned = next_pc[1:0] != 2'b0;
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//fetch_hit = (next_pc[31:2] == data_tag[31:2]);
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fetch_hit = (fetch_addr[31:2] == data_tag[31:2]);
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end
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always_comb
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begin
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fetch_fsm_ns = fetch_fsm_cs;
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fetch_addr_n = {next_pc[31:2], 2'b0};
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sample_addr = 1'b0;
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pc_if_offset_n = pc_if_offset; //1'b0;
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//sample_offset = 1'b0;
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ack_o = 1'b0;
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req_int = 1'b0;
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force_nop_int = 1'b0;
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bypass_data_reg = 1'b0;
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unique case (fetch_fsm_cs)
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INVALID:
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begin
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if (do_fetch) begin
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if (force_nop_i) begin
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force_nop_int = 1'b1;
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ack_o = 1'b1;
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end else begin
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fetch_fsm_ns = FETCH;
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end
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end
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end
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VALID:
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begin
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if (do_fetch) begin
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if (force_nop_i) begin
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force_nop_int = 1'b1;
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ack_o = 1'b1;
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end else begin
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if (fetch_hit) begin
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if (pc_if_offset) begin
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fetch_addr_n = last_fetch_addr + 4;
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sample_addr = 1'b1;
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if (is_compressed[1]) begin
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pc_if_offset_n = 1'b0;
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ack_o = 1'b1;
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end else begin
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fetch_fsm_ns = FETCH_NEXT;
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end
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end else begin
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ack_o = 1'b1;
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if (is_compressed[0]) begin
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pc_if_offset_n = 1'b1;
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end else begin
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fetch_addr_n = last_fetch_addr + 4;
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sample_addr = 1'b1;
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end
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end
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end else begin
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// fetch single requested word
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sample_addr = 1'b1;
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fetch_fsm_ns = FETCH;
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end
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// check if request can be served from local cache
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if (fetch_unaligned && fetch_hit) begin
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//if (is_compressed[1]) begin
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// // instruction is compressed and can be served from cache
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// pc_if_offset_n = 1'b1;
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// fetch_fsm_ns = SERVE_OFFSET;
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//end else begin
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// // fetch next instruction
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// fetch_addr_n = last_fetch_addr + 4;
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// sample_addr = 1'b1;
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// fetch_fsm_ns = FETCH_NEXT;
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//end
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end else if (fetch_unaligned) begin
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// fetch two words
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//sample_addr = 1'b1;
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//fetch_fsm_ns = FETCH;
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end else begin
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//// fetch single requested word
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//sample_addr = 1'b1;
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//fetch_fsm_ns = FETCH;
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end
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//fetch_fsm_ns = FETCH;
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end
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end
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end
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SERVE_OFFSET:
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begin
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ack_o = 1'b1;
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fetch_fsm_ns = VALID;
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end
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FETCH:
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begin
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req_int = 1'b1;
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if (ack_int) begin
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req_int = 1'b0; // TODO: Maybe only assert req_int before going into FETCH state
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bypass_data_reg = 1'b1;
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//ack_o = 1'b1;
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fetch_fsm_ns = VALID;
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end
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end
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FETCH_NEXT:
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begin
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req_int = 1'b1;
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if (ack_int) begin
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req_int = 1'b0; // TODO: Maybe only assert req_int before going into FETCH state
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bypass_data_reg = 1'b1;
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ack_o = 1'b1;
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fetch_fsm_ns = VALID;
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sample_addr = 1'b1;
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end
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end
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endcase
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if (pc_mux_boot_i) begin
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sample_addr = 1'b1;
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fetch_fsm_ns = INVALID;
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end
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end
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@ -153,7 +366,7 @@ module if_stage
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`PC_HWLOOP: next_pc = pc_from_hwloop_i; // PC is taken from hwloop start addr
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default:
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begin
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next_pc = current_pc_if_o;
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next_pc = {boot_addr_i[31:5], `EXC_OFF_RST};
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// synopsys translate_off
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$display("%t: Illegal pc_mux_sel value (%0d)!", $time, pc_mux_sel_i);
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// synopsys translate_on
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@ -169,7 +382,6 @@ module if_stage
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next_pc = jump_target_i;
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else
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next_pc = incr_pc;
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//next_pc = current_pc_if_o;
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end
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if (pc_mux_boot_i)
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@ -177,103 +389,6 @@ module if_stage
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end
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always_comb
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begin
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NS = CS;
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req_int = 1'b0;
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addr_int = '0;
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ack_o = 1'b0;
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force_nop_int = 1'b0;
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unique case (CS)
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IDLE:
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begin
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if (req_i) begin
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if (jump_in_id_i == 2'b0) begin
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if (force_nop_i) begin
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force_nop_int = 1'b1;
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ack_o = 1'b1;
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end else begin
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// no branch, do normal fetch
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req_int = 1'b1;
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addr_int = next_pc;
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if (stall_if_i) begin
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NS = FETCH_STALLED;
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end else begin
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NS = FETCH_UNSTALLED;
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end
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end
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end
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else
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begin
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// wait for branch decision / jump target
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force_nop_int = 1'b1;
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ack_o = 1'b1;
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NS = WAIT_BRANCH;
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end
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end
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end
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WAIT_BRANCH:
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begin
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if (jump_in_ex_i != 2'b0) begin
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req_int = 1'b1;
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addr_int = next_pc;
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if (stall_if_i) begin
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NS = FETCH_STALLED;
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end else begin
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NS = FETCH_UNSTALLED;
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end
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end
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end
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FETCH_STALLED,
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FETCH_UNSTALLED:
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begin
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if (ack_int) begin
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NS = IDLE;
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ack_o = 1'b1;
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if (stall_if_i) begin
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if (CS == FETCH_STALLED) begin
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// already fetched instruction for after stall
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NS = WAIT_IF_STALL;
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end
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end
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end
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end
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WAIT_IF_STALL:
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begin
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NS = IDLE;
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ack_o = 1'b1;
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if (stall_if_i)
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NS = WAIT_IF_STALL;
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end
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default:
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begin
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$display("%t: invalid state", $time);
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end
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endcase
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end
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0)
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begin
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CS <= IDLE;
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end
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else
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begin
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CS <= NS;
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end
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end
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// cache fetch interface
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instr_core_interface instr_core_if_i
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(
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@ -282,7 +397,7 @@ module if_stage
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.req_i ( req_int ),
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.ack_o ( ack_int ),
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.addr_i ( addr_int ),
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.addr_i ( fetch_addr ),
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.rdata_o ( rdata_int ),
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.instr_req_o ( instr_req_o ),
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@ -304,23 +419,24 @@ module if_stage
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begin : IF_PIPELINE
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if (rst_n == 1'b0)
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begin
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current_pc_if_o <= 32'h0;
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//current_pc_if_o <= 32'h0;
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end
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else
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begin
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if (pc_mux_boot_i == 1'b1)
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//if (pc_mux_boot_i == 1'b1)
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//begin
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// // set PC to reset vector
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// current_pc_if_o <= {boot_addr_i[31:5], `EXC_OFF_RST};
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//end
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//else if (dbg_set_npc == 1'b1)
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//begin
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// // debug units sets NPC, PC_MUX_SEL holds this value
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// current_pc_if_o <= dbg_pc_from_npc;
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//end
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//else if (stall_if_i == 1'b0)
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if (stall_if_i == 1'b0)
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begin
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// set PC to reset vector
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current_pc_if_o <= {boot_addr_i[31:5], `EXC_OFF_RST};
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end
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else if (dbg_set_npc == 1'b1)
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begin
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// debug units sets NPC, PC_MUX_SEL holds this value
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current_pc_if_o <= dbg_pc_from_npc;
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end
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else if (stall_if_i == 1'b0)
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begin
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current_pc_if_o <= last_fetch_addr;
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//current_pc_if_o <= last_fetch_addr;
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end
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end
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end
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@ -338,8 +454,7 @@ module if_stage
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if (stall_id_i == 1'b0)
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begin : ENABLED_PIPE
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instr_rdata_id_o <= instr_rdata_int;
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//current_pc_id_o <= current_pc_if_o;
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current_pc_id_o <= last_fetch_addr;
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current_pc_id_o <= current_pc_if_o;
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end
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end
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end
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