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Update google_riscv-dv to google/riscv-dv@e3e1e30 (#349)
Update code from upstream repository https://github.com/google/riscv- dv to revision e3e1e308cfc3d718aeb94bb3463371979d9a31ae * Disable full trace in the run script (google/riscv-dv#180) (taoliug) * Fix spike logging issue (google/riscv-dv#179) (taoliug) * Add functional coverage for HINT instructions (google/riscv-dv#177) (taoliug) * Add functional coverage for various hazard conditions (google/riscv- dv#176) (taoliug)
This commit is contained in:
udinator
GitHub
parent
1e8381bfa1
commit
83178c69f9
7 changed files with 183 additions and 48 deletions
2
vendor/google_riscv-dv.lock.hjson
vendored
2
vendor/google_riscv-dv.lock.hjson
vendored
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@ -9,6 +9,6 @@
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upstream:
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{
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url: https://github.com/google/riscv-dv
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rev: 44505927a70a6234b996d15f2e51bd1e2632b68e
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rev: e3e1e308cfc3d718aeb94bb3463371979d9a31ae
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}
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}
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@ -39,7 +39,7 @@ HEX_RE = re.compile(r"^0x")
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LOGGER = logging.getLogger()
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def process_spike_sim_log(spike_log, csv, full_trace = 1):
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def process_spike_sim_log(spike_log, csv, full_trace = 0):
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"""Process SPIKE simulation log.
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Extract instruction and affected register information from spike simulation
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@ -50,7 +50,7 @@ def process_spike_sim_log(spike_log, csv, full_trace = 1):
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spike_instr = ""
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# Remove all the init spike boot instructions
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cmd = ("sed -i '/3 0x0000000000001010/,$!d' %s" % spike_log)
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cmd = ("sed -i '/core.*0x0000000000001010/,$!d' %s" % spike_log)
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os.system(cmd)
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# Remove all instructions after ecall (end of program excecution)
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cmd = ("sed -i '/ecall/q' %s" % spike_log)
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@ -363,7 +363,8 @@ def assign_operand(trace, operands, gpr):
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trace.rd = 'zero'
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trace.rd_val = '0'
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trace.rs1 = operands[0]
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trace.rs1_val = gpr[trace.rs1]
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if trace.rs1 in gpr:
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trace.rs1_val = gpr[trace.rs1]
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elif trace.instr in ['li']:
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trace.instr = 'li'
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elif trace.instr[0:2] in ['lr', 'am', 'sc']:
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@ -111,12 +111,23 @@ class riscv_illegal_instr extends uvm_object;
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constraint hint_instr_c {
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if (exception == kHintInstr) {
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// C.ADDI
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((c_msb == 3'b000) && (c_op == 2'b01) && ({instr_bin[12], instr_bin[6:2]} == 6'b0)) ||
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// C.LI
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((c_msb == 3'b010) && (c_op == 2'b01) && (instr_bin[11:7] == 5'b0)) ||
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// C.SRAI64, C.SRLI64
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((c_msb == 3'b100) && (c_op == 2'b01) && (instr_bin[12:11] == 2'b00) &&
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(instr_bin[6:2] == 5'b0)) ||
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// C.LUI
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((c_msb == 3'b011) && (c_op == 2'b01) && (instr_bin[11:7] == 5'b0) &&
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({instr_bin[12], instr_bin[6:2]} != 6'b0)) ||
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((c_msb == 3'b100) && (c_op == 2'b10) && (instr_bin[12:7] == 6'b0) &&
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// C.SLLI
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((c_msb == 3'b000) && (c_op == 2'b10) && (instr_bin[11:7] == 5'b0)) ||
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// C.SLLI64
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((c_msb == 3'b000) && (c_op == 2'b10) && (instr_bin[11:7] != 5'b0) && !instr_bin[12] &&
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(instr_bin[6:2] == 0)) ||
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// C.ADD
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((c_msb == 3'b100) && (c_op == 2'b10) && (instr_bin[11:7] == 5'b0) && instr_bin[12] &&
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(instr_bin[6:2] != 0));
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}
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}
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@ -19,6 +19,7 @@ class riscv_instr_cov_item extends riscv_instr_base;
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rand bit [XLEN-1:0] rs1_value;
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rand bit [XLEN-1:0] rs2_value;
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rand bit [XLEN-1:0] rd_value;
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bit [31:0] binary;
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bit [XLEN-1:0] pc;
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bit [XLEN-1:0] mem_addr;
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@ -30,6 +31,8 @@ class riscv_instr_cov_item extends riscv_instr_base;
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operand_sign_e rs2_sign;
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operand_sign_e imm_sign;
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operand_sign_e rd_sign;
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hazard_e gpr_hazard;
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hazard_e lsu_hazard;
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special_val_e rs1_special_val;
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special_val_e rs2_special_val;
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special_val_e rd_special_val;
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@ -184,6 +187,41 @@ class riscv_instr_cov_item extends riscv_instr_base;
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return DIFFERENT;
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endfunction
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function void check_hazard_condition(riscv_instr_cov_item pre_instr);
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riscv_reg_t gpr;
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if (pre_instr.has_rd) begin
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if ((has_rs1 && (rs1 == pre_instr.rd)) || (has_rs2 && (rs2 == pre_instr.rd))) begin
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gpr_hazard = RAW_HAZARD;
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end else if (has_rd && (rd == pre_instr.rd)) begin
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gpr_hazard = WAW_HAZARD;
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end else if (has_rd && ((pre_instr.has_rs1 && (pre_instr.rs1 == rd)) ||
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(pre_instr.has_rs2 && (pre_instr.rs2 == rd)))) begin
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gpr_hazard = WAR_HAZARD;
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end else begin
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gpr_hazard = NO_HAZARD;
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end
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end
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if (category == LOAD) begin
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if ((pre_instr.category == STORE) && (pre_instr.mem_addr == mem_addr)) begin
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lsu_hazard = RAW_HAZARD;
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end else begin
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lsu_hazard = NO_HAZARD;
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end
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end
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if (category == STORE) begin
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if ((pre_instr.category == STORE) && (pre_instr.mem_addr == mem_addr)) begin
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lsu_hazard = WAW_HAZARD;
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end else if ((pre_instr.category == LOAD) && (pre_instr.mem_addr == mem_addr)) begin
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lsu_hazard = WAR_HAZARD;
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end else begin
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lsu_hazard = NO_HAZARD;
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end
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end
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`uvm_info(`gfn, $sformatf("Pre:%0s, Cur:%0s, Hazard: %0s/%0s",
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pre_instr.convert2asm(), this.convert2asm(),
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gpr_hazard.name(), lsu_hazard.name()), UVM_FULL)
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endfunction
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virtual function void sample_cov();
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pre_sample();
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endfunction
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@ -3,86 +3,114 @@
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`define R_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_rs1 : coverpoint instr.rs1; \
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cp_rs2 : coverpoint instr.rs2; \
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cp_rd : coverpoint instr.rd; \
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cp_rs1_sign : coverpoint instr.rs1_sign; \
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cp_rs2_sign : coverpoint instr.rs2_sign; \
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cp_rd_sign : coverpoint instr.rd_sign;
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cp_rs1 : coverpoint instr.rs1; \
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cp_rs2 : coverpoint instr.rs2; \
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cp_rd : coverpoint instr.rd; \
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cp_rs1_sign : coverpoint instr.rs1_sign; \
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cp_rs2_sign : coverpoint instr.rs2_sign; \
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cp_rd_sign : coverpoint instr.rd_sign; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard; \
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`define CMP_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_rs1 : coverpoint instr.rs1; \
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cp_rd : coverpoint instr.rd; \
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cp_rs1_sign : coverpoint instr.rs1_sign; \
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cp_result : coverpoint instr.rd_value[0];
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cp_rs1 : coverpoint instr.rs1; \
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cp_rd : coverpoint instr.rd; \
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cp_rs1_sign : coverpoint instr.rs1_sign; \
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cp_result : coverpoint instr.rd_value[0]; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard; \
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`define SB_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_rs1 : coverpoint instr.rs1; \
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cp_rs2 : coverpoint instr.rs2; \
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cp_rs1_sign : coverpoint instr.rs1_sign; \
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cp_rs2_sign : coverpoint instr.rs2_sign; \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_branch_hit : coverpoint instr.branch_hit; \
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cp_sign_cross : cross cp_rs1_sign, cp_rs2_sign, cp_imm_sign;
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cp_rs1 : coverpoint instr.rs1; \
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cp_rs2 : coverpoint instr.rs2; \
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cp_rs1_sign : coverpoint instr.rs1_sign; \
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cp_rs2_sign : coverpoint instr.rs2_sign; \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_branch_hit : coverpoint instr.branch_hit; \
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cp_sign_cross : cross cp_rs1_sign, cp_rs2_sign, cp_imm_sign; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard { \
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bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
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}
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`define STORE_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_rs1 : coverpoint instr.rs1; \
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cp_rs2 : coverpoint instr.rs2; \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_rs1 : coverpoint instr.rs1; \
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cp_rs2 : coverpoint instr.rs2; \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard { \
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bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
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} \
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cp_lsu_harzard : coverpoint instr.lsu_hazard { \
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bins valid_hazard[] = {NO_HAZARD, WAR_HAZARD, WAW_HAZARD}; \
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}
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`define LOAD_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_rs1 : coverpoint instr.rs1; \
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cp_rd : coverpoint instr.rd; \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_rs1 : coverpoint instr.rs1; \
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cp_rd : coverpoint instr.rd; \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard; \
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cp_lsu_harzard : coverpoint instr.lsu_hazard { \
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bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
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}
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`define I_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_rs1 : coverpoint instr.rs1; \
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cp_rd : coverpoint instr.rd; \
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cp_rs1_sign : coverpoint instr.rs1_sign; \
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cp_rd_sign : coverpoint instr.rd_sign; \
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cp_imm_sign : coverpoint instr.imm_sign;
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cp_rs1 : coverpoint instr.rs1; \
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cp_rd : coverpoint instr.rd; \
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cp_rs1_sign : coverpoint instr.rs1_sign; \
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cp_rd_sign : coverpoint instr.rd_sign; \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard;
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`define U_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_rd : coverpoint instr.rd; \
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cp_rd_sign : coverpoint instr.rd_sign; \
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cp_imm_sign : coverpoint instr.imm_sign;
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cp_rd : coverpoint instr.rd; \
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cp_rd_sign : coverpoint instr.rd_sign; \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard;
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`define CSR_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_csr : coverpoint instr.csr { \
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cp_csr : coverpoint instr.csr { \
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bins csr[] = cp_csr with (is_implemented_csr(item)); \
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} \
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cp_rs1 : coverpoint instr.rs1; \
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cp_rd : coverpoint instr.rd;
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cp_rs1 : coverpoint instr.rs1; \
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cp_rd : coverpoint instr.rd; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard;
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`define CR_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_rs2 : coverpoint instr.rs2; \
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cp_rd : coverpoint instr.rd; \
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cp_rs2_sign : coverpoint instr.rs2_sign;
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cp_rs2 : coverpoint instr.rs2; \
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cp_rd : coverpoint instr.rd; \
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cp_rs2_sign : coverpoint instr.rs2_sign; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard;
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`define CI_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_rd : coverpoint instr.rd; \
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cp_imm_sign : coverpoint instr.imm_sign;
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard { \
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bins valid_hazard[] = {NO_HAZARD, WAR_HAZARD, WAW_HAZARD}; \
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}
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`define CSS_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_rs2 : coverpoint instr.rs2; \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_rs2_sign : coverpoint instr.rs2_sign;
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cp_rs2_sign : coverpoint instr.rs2_sign; \
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cp_gpr_harzard : coverpoint instr.gpr_hazard { \
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bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
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}
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`define CIW_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_rd : coverpoint instr.rd { \
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bins gpr[] = cp_rd with (is_compressed_gpr(riscv_reg_t'(item))); \
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} \
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cp_gpr_harzard : coverpoint instr.gpr_hazard { \
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bins valid_hazard[] = {NO_HAZARD, WAR_HAZARD, WAW_HAZARD}; \
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}
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`define CL_INSTR_CG_BEGIN(INSTR_NAME) \
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@ -93,6 +121,10 @@
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} \
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cp_rd : coverpoint instr.rd { \
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bins gpr[] = cp_rd with (is_compressed_gpr(riscv_reg_t'(item))); \
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} \
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cp_gpr_harzard : coverpoint instr.gpr_hazard; \
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cp_lsu_harzard : coverpoint instr.lsu_hazard { \
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bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
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}
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`define CS_INSTR_CG_BEGIN(INSTR_NAME) \
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@ -103,13 +135,23 @@
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} \
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cp_rs2 : coverpoint instr.rs2 { \
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bins gpr[] = cp_rs2 with (is_compressed_gpr(riscv_reg_t'(item))); \
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} \
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cp_gpr_harzard : coverpoint instr.gpr_hazard { \
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bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
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} \
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cp_lsu_harzard : coverpoint instr.lsu_hazard { \
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bins valid_hazard[] = {NO_HAZARD, WAR_HAZARD, WAW_HAZARD}; \
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}
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`define CB_INSTR_CG_BEGIN(INSTR_NAME) \
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`INSTR_CG_BEGIN(INSTR_NAME) \
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cp_imm_sign : coverpoint instr.imm_sign; \
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cp_rs1 : coverpoint instr.rs1 { \
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bins gpr[] = cp_rs1 with (is_compressed_gpr(riscv_reg_t'(item))); \
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} \
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cp_gpr_harzard : coverpoint instr.gpr_hazard { \
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bins valid_hazard[] = {NO_HAZARD, RAW_HAZARD}; \
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}
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`define CJ_INSTR_CG_BEGIN(INSTR_NAME) \
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@ -122,8 +164,8 @@ class riscv_instr_cover_group#(privileged_reg_t implemented_pcsr[] =
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riscv_instr_pkg::implemented_csr);
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riscv_instr_gen_config cfg;
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riscv_instr_name_t instr_name;
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riscv_instr_name_t pre_instr_name;
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riscv_instr_cov_item cur_instr;
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riscv_instr_cov_item pre_instr;
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riscv_instr_name_t instr_list[$];
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int unsigned instr_cnt;
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int unsigned branch_instr_cnt;
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@ -520,6 +562,32 @@ class riscv_instr_cover_group#(privileged_reg_t implemented_pcsr[] =
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`CR_INSTR_CG_BEGIN(c_addw)
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`CG_END
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`INSTR_CG_BEGIN(hint)
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cp_hint : coverpoint instr.binary[15:0] {
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wildcard bins addi = {16'b0000_1xxx_x000_0001,
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16'b0000_x1xx_x000_0001,
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16'b0000_xx1x_x000_0001,
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16'b0000_xxx1_x000_0001,
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16'b0000_xxxx_1000_0001};
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wildcard bins li = {16'b010x_0000_0xxx_xx01};
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wildcard bins lui = {16'b011x_0000_0xxx_xx01};
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wildcard bins srli64 = {16'b1000_00xx_x000_0001};
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wildcard bins srai64 = {16'b1000_01xx_x000_0001};
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wildcard bins slli = {16'b000x_0000_0xxx_xx10};
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wildcard bins slli64 = {16'b0000_xxxx_x000_0010};
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wildcard bins mv = {16'b1000_0000_01xx_xx10,
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16'b1000_0000_0x1x_xx10,
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16'b1000_0000_0xx1_xx10,
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16'b1000_0000_0xxx_1x10,
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16'b1000_0000_0xxx_x110};
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wildcard bins add = {16'b1001_0000_01xx_xx10,
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16'b1001_0000_0x1x_xx10,
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16'b1001_0000_0xx1_xx10,
|
||||
16'b1001_0000_0xxx_1x10,
|
||||
16'b1001_0000_0xxx_x110};
|
||||
}
|
||||
`CG_END
|
||||
|
||||
// Branch hit history
|
||||
covergroup branch_hit_history_cg;
|
||||
coverpoint branch_hit_history;
|
||||
|
|
@ -549,7 +617,10 @@ class riscv_instr_cover_group#(privileged_reg_t implemented_pcsr[] =
|
|||
|
||||
function new(riscv_instr_gen_config cfg);
|
||||
this.cfg = cfg;
|
||||
cur_instr = riscv_instr_cov_item::type_id::create("cur_instr");
|
||||
pre_instr = riscv_instr_cov_item::type_id::create("pre_instr");
|
||||
build_instr_list();
|
||||
hint_cg = new();
|
||||
// RV32I instruction functional coverage instantiation
|
||||
add_cg = new();
|
||||
sub_cg = new();
|
||||
|
|
@ -663,9 +734,13 @@ class riscv_instr_cover_group#(privileged_reg_t implemented_pcsr[] =
|
|||
endfunction
|
||||
|
||||
function void sample(riscv_instr_cov_item instr);
|
||||
pre_instr_name = instr_name;
|
||||
instr_name = instr.instr_name;
|
||||
instr_cnt += 1;
|
||||
if (instr_cnt > 1) begin
|
||||
instr.check_hazard_condition(pre_instr);
|
||||
end
|
||||
if (instr.binary[1:0] != 2'b11) begin
|
||||
hint_cg.sample(instr);
|
||||
end
|
||||
case (instr.instr_name)
|
||||
ADD : add_cg.sample(instr);
|
||||
SUB : sub_cg.sample(instr);
|
||||
|
|
@ -775,6 +850,8 @@ class riscv_instr_cover_group#(privileged_reg_t implemented_pcsr[] =
|
|||
if (instr_cnt > 1) begin
|
||||
// instr_trans_cg.sample();
|
||||
end
|
||||
pre_instr.copy_base_instr(instr);
|
||||
pre_instr.mem_addr = instr.mem_addr;
|
||||
endfunction
|
||||
|
||||
// Check if the privileged CSR is implemented
|
||||
|
|
|
|||
|
|
@ -685,6 +685,13 @@ package riscv_instr_pkg;
|
|||
MISA_EXT_Z
|
||||
} misa_ext_t;
|
||||
|
||||
typedef enum bit [1:0] {
|
||||
NO_HAZARD,
|
||||
RAW_HAZARD,
|
||||
WAR_HAZARD,
|
||||
WAW_HAZARD
|
||||
} hazard_e;
|
||||
|
||||
`include "riscv_core_setting.sv"
|
||||
|
||||
typedef bit [15:0] program_id_t;
|
||||
|
|
|
|||
|
|
@ -122,6 +122,7 @@ class riscv_instr_cov_test extends uvm_test;
|
|||
riscv_reg_t gpr;
|
||||
privileged_reg_t preg;
|
||||
get_val(trace["addr"], instr.pc);
|
||||
get_val(trace["binary"], instr.binary);
|
||||
instr.trace = trace["instr_str"];
|
||||
if (instr.instr_name inside {ECALL, EBREAK, FENCE, FENCE_I, NOP,
|
||||
C_NOP, WFI, MRET, C_EBREAK}) begin
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue