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Update SCONTEXT address, add MSCONTEXT csr to match riscv_debug 1.0

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Observing the spec change:
RISC-V Debug Support Version 1.0.0-STABLE
1.2.1.4 New Features from 0.13 to 1.0
> 8. Move scontext, renaming original to mscontext, and create hcontext. #535

MSCONTEXT is a backwards-compatible alias to SCONTEXT
In Ibex, SCONTEXT is a read-only zero register. Hence MSCONTEXT has the same behaviour.
This commit is contained in:
Harry Callahan 2022-10-04 16:46:00 +01:00
parent 1cdd403564
commit 836bd67531
2 changed files with 7 additions and 1 deletions
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4
rtl/ibex_cs_registers.sv
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@ -523,6 +523,10 @@ module ibex_cs_registers #(
csr_rdata_int = '0;
illegal_csr = ~DbgTriggerEn;
end
CSR_MSCONTEXT: begin
csr_rdata_int = '0;
illegal_csr = ~DbgTriggerEn;
end
// Custom CSR for controlling CPU features and reporting CPU status
CSR_CPUCTRLSTS: begin

4
rtl/ibex_pkg.sv
View file

@ -471,6 +471,8 @@ package ibex_pkg;
CSR_PMPADDR14 = 12'h3BE,
CSR_PMPADDR15 = 12'h3BF,
CSR_SCONTEXT = 12'h5A8,
// ePMP control
CSR_MSECCFG = 12'h747,
CSR_MSECCFGH = 12'h757,
@ -481,7 +483,7 @@ package ibex_pkg;
CSR_TDATA2 = 12'h7A2,
CSR_TDATA3 = 12'h7A3,
CSR_MCONTEXT = 12'h7A8,
CSR_SCONTEXT = 12'h7AA,
CSR_MSCONTEXT = 12'h7AA,
// Debug/trace
CSR_DCSR = 12'h7b0,