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Fix illegal RVC instructions not causing exceptions

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This commit is contained in:
Sven Stucki 2015-08-26 16:40:22 +02:00
parent 8bdb45799f
commit 84bec09a64
2 changed files with 22 additions and 11 deletions
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23
controller.sv
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@ -99,6 +99,7 @@ module controller
input logic irq_present_i, // there is an IRQ, so if we are sleeping we should wake up now
// Exception Controller Signals
input logic illegal_c_insn_i, // compressed instruction decode failed
output logic illegal_insn_o, // illegal instruction encountered
output logic trap_insn_o, // trap instruction encountered
output logic pipe_flush_o, // pipe flush requested by controller
@ -241,6 +242,7 @@ module controller
wrong_branch_taken_o = 1'b0;
take_branch_o = 1'b0;
`endif
unique case (instr_rdata_i[6:0])
//////////////////////////////////////
@ -839,6 +841,9 @@ module controller
set_flag = 1'b1; // set the flag for lv32.all_* and lv32.any_*
end
*/
////////////////////////////////////////////////
// ____ ____ _____ ____ ___ _ _ //
// / ___|| _ \| ____/ ___|_ _| / \ | | //
@ -848,13 +853,10 @@ module controller
// //
////////////////////////////////////////////////
*/
`OPCODE_SYSTEM: begin
if (instr_rdata_i[14:12] == 3'b000)
begin
// non CSR realted SYSTEM instructions
// non CSR related SYSTEM instructions
unique case (instr_rdata_i) inside
`INSTR_EBREAK: begin
// debugger trap
@ -869,19 +871,21 @@ module controller
// flush pipeline
pipe_flush_o = 1'b1;
end
default: illegal_insn_o = 1'b1;
default: begin
illegal_insn_o = 1'b1;
end
endcase // unique case (instr_rdata_i)
end
else
begin
// instructions to read/modify CSRs
// instruction to read/modify CSR
csr_access_o = 1'b1;
regfile_alu_we = 1'b1;
alu_op_b_mux_sel_o = `OP_B_IMM;
immediate_mux_sel_o = `IMM_I; // CSR address is encoded in I imm
if (instr_rdata_i[14] == 1'b1) begin
// rs1 field is immediate
// rs1 field is used as immediate
alu_op_a_mux_sel_o = `OP_A_ZIMM;
end else begin
rega_used = 1'b1;
@ -978,6 +982,11 @@ module controller
end
endcase
// make sure invalid compressed instruction causes an exception
if (illegal_c_insn_i) begin
illegal_insn_o = 1'b1;
end
// synopsys translate_off
if (illegal_insn_o == 1'b1) begin
$display("%t: Illegal instruction (core %0d):", $time, riscv_core.core_id_i);

10
id_stage.sv
View file

@ -189,6 +189,7 @@ module id_stage
assign jump_in_ex_o = jump_in_ex;
logic illegal_insn;
logic illegal_c_insn;
logic trap_insn;
logic trap_hit;
logic pipe_flush;
@ -278,10 +279,10 @@ module id_stage
// compressed instruction decoding
compressed_decoder compressed_decoder_i (
.instr_i (instr_rdata_i),
.instr_o (instr),
.is_compressed_o (compressed_instr_o),
.illegal_instr_o (illegal_compressed_instr)
.instr_i ( instr_rdata_i ),
.instr_o ( instr ),
.is_compressed_o ( compressed_instr_o ),
.illegal_instr_o ( illelgal_c_insn )
);
@ -596,6 +597,7 @@ module id_stage
.irq_present_i ( irq_present ),
// Exception Controller Signals
.illegal_c_insn_i ( illegal_c_insn ),
.illegal_insn_o ( illegal_insn ),
.trap_insn_o ( trap_insn ),
.pipe_flush_o ( pipe_flush ),