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https://github.com/lowRISC/ibex.git
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[syn] Update path to prim_assert
- Also remove unsigned keyword stripping which is no longer required Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
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parent
bfa531c039
commit
85ce3874eb
2 changed files with 2 additions and 8 deletions
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@ -14,7 +14,7 @@ OUTDIR := build
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# Source directory relative to this Makefile
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# Source directory relative to this Makefile
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SRC_DIR := ../rtl
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SRC_DIR := ../rtl
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# Include directory relative to this Makefile
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# Include directory relative to this Makefile
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INC_DIR := ../shared/rtl
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INC_DIR := ../vendor/lowrisc_ip/prim/rtl
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# SystemVerilog sources of Ibex
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# SystemVerilog sources of Ibex
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SRCS_SV ?= $(SRC_DIR)/ibex_alu.sv \
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SRCS_SV ?= $(SRC_DIR)/ibex_alu.sv \
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@ -31,15 +31,9 @@ for file in ../rtl/*.sv; do
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sv2v \
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sv2v \
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--define=SYNTHESIS \
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--define=SYNTHESIS \
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../rtl/*_pkg.sv \
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../rtl/*_pkg.sv \
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-I../shared/rtl \
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-I../vendor/lowrisc_ip/prim/rtl \
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$file \
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$file \
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> $LR_SYNTH_OUT_DIR/generated/${module}.v
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> $LR_SYNTH_OUT_DIR/generated/${module}.v
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# TODO: eventually remove below hack. It removes "unsigned" from params
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# because Yosys doesn't support unsigned parameters
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sed -i 's/parameter unsigned/parameter/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
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sed -i 's/localparam unsigned/localparam/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
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sed -i 's/reg unsigned/reg/g' $LR_SYNTH_OUT_DIR/generated/${module}.v
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done
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done
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# remove generated *pkg.v files (they are empty files and not needed)
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# remove generated *pkg.v files (they are empty files and not needed)
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