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Add many ALU instructions from OR10N
This commit is contained in:
Sven Stucki
parent
715265d61d
commit
88fb2adac3
3 changed files with 46 additions and 196 deletions
20
alu.sv
20
alu.sv
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@ -284,13 +284,14 @@ module alu
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cmp_sign_mode[3:0] = 4'b0000; // unsigned mode
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// signed mode
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if ((operator_i == `ALU_GTS) ||
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(operator_i == `ALU_GES) ||
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(operator_i == `ALU_LTS) ||
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(operator_i == `ALU_SLTS) ||
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(operator_i == `ALU_LES) ||
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(operator_i == `ALU_MAX) ||
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(operator_i == `ALU_MIN) ||
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if ((operator_i == `ALU_GTS) ||
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(operator_i == `ALU_GES) ||
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(operator_i == `ALU_LTS) ||
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(operator_i == `ALU_SLTS) ||
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(operator_i == `ALU_SLETS) ||
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(operator_i == `ALU_LES) ||
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(operator_i == `ALU_MAX) ||
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(operator_i == `ALU_MIN) ||
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(operator_i == `ALU_ABS))
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begin
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case (vector_mode_i)
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@ -356,6 +357,8 @@ module alu
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`ALU_GES, `ALU_GEU: cmp_result = is_greater | is_equal;
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`ALU_LTS, `ALU_SLTS,
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`ALU_LTU, `ALU_SLTU: cmp_result = ~(is_greater | is_equal);
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`ALU_SLETS,
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`ALU_SLETU,
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`ALU_LES, `ALU_LEU: cmp_result = ~is_greater;
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default:; // nothing to do
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endcase //~case(operator_i)
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@ -590,6 +593,9 @@ module alu
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// Set Lower Than Operations (result = 1, if a < b)
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`ALU_SLTS, `ALU_SLTU: result_o = {31'b0, cmp_result[0]};
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// Set Lower Equal Than Operations (result = 1, if a <= b)
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`ALU_SLETS, `ALU_SLETU: result_o = {31'b0, cmp_result[0]};
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`ALU_FF1: result_o = {26'h0, ff1_result};
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`ALU_FL1: result_o = {26'h0, fl1_result};
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`ALU_CLB: result_o = {26'h0, clb_result};
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220
decoder.sv
220
decoder.sv
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@ -414,23 +414,49 @@ module riscv_decoder
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rega_used_o = 1'b1;
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regb_used_o = 1'b1;
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if (instr_rdata_i[28])
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regb_used_o = 1'b0;
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unique case ({instr_rdata_i[31:25], instr_rdata_i[14:12]})
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// RV32I ALU operations
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{7'b000_0000, 3'b000}: alu_operator = `ALU_ADD; // Add
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{7'b010_0000, 3'b000}: alu_operator = `ALU_SUB; // Sub
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{7'b000_0000, 3'b010}: alu_operator = `ALU_SLTS; // Set Lower Than
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{7'b000_0000, 3'b011}: alu_operator = `ALU_SLTU; // Set Lower Than Unsigned
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{7'b000_0000, 3'b100}: alu_operator = `ALU_XOR; // Xor
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{7'b000_0000, 3'b110}: alu_operator = `ALU_OR; // Or
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{7'b000_0000, 3'b111}: alu_operator = `ALU_AND; // And
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{7'b000_0000, 3'b001}: alu_operator = `ALU_SLL; // Shift Left Logical
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{7'b000_0000, 3'b101}: alu_operator = `ALU_SRL; // Shift Right Logical
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{7'b010_0000, 3'b101}: alu_operator = `ALU_SRA; // Shift Right Arithmetic
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// supported RV32M instructions
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{7'b000_0001, 3'b000}: mult_en = 1'b1; // Multiplication
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// PULP specific instructions
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{7'b000_0010, 3'b000}: alu_operator = `ALU_AVG; // Average
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{7'b000_0010, 3'b001}: alu_operator = `ALU_AVGU; // Average Unsigned
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{7'b000_0010, 3'b010}: alu_operator = `ALU_SLETS; // Set Lower Equal Than
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{7'b000_0010, 3'b011}: alu_operator = `ALU_SLETU; // Set Lower Equal Than Unsigned
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{7'b000_0010, 3'b100}: alu_operator = `ALU_MIN; // Min
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{7'b000_0010, 3'b101}: alu_operator = `ALU_MINU; // Min Unsigned
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{7'b000_0010, 3'b110}: alu_operator = `ALU_MAX; // Max
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{7'b000_0010, 3'b111}: alu_operator = `ALU_MAXU; // Max Unsigned
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{7'b000_0100, 3'b101}: alu_operator = `ALU_ROR; // Rotate Right
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// PULP specific instructions using only one source register
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{7'b000_1000, 3'b000}: alu_operator = `ALU_FF1; // Find First 1
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{7'b000_1000, 3'b001}: alu_operator = `ALU_FL1; // Find Last 1
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{7'b000_1000, 3'b010}: alu_operator = `ALU_CLB; // Count Leading Bits
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{7'b000_1000, 3'b011}: alu_operator = `ALU_CNT; // Count set bits (popcount)
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{7'b000_1000, 3'b100}: alu_operator = `ALU_EXTHS; // Sign-extend Half-word
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{7'b000_1000, 3'b101}: alu_operator = `ALU_EXTHZ; // Zero-extend Half-word
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{7'b000_1000, 3'b110}: alu_operator = `ALU_EXTBS; // Sign-extend Byte
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{7'b000_1000, 3'b111}: alu_operator = `ALU_EXTBZ; // Zero-extend Byte
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{7'b000_1010, 3'b000}: alu_operator = `ALU_ABS; // Absolute
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default: begin
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regfile_alu_we = 1'b0;
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illegal_insn_o = 1'b1;
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@ -438,18 +464,14 @@ module riscv_decoder
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endcase
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end
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`OPCODE_PULP_OP: begin // PULP specific ALU instructions
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mult_en = 1'b1;
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mult_mac_en = 1'b1;
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`OPCODE_PULP_OP: begin // PULP specific ALU instructions with three source operands
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regfile_alu_we = 1'b1;
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rega_used_o = 1'b1;
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regb_used_o = 1'b1;
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regc_used_o = 1'b1;
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case (instr_rdata_i[14:12])
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3'b000: begin // MAC
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regc_used_o = 1'b1;
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mult_en = 1'b1;
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mult_mac_en = 1'b1;
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end
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@ -458,8 +480,6 @@ module riscv_decoder
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3'b101,
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3'b110,
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3'b111: begin // MAC with subword selection
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regc_used_o = 1'b1;
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vector_mode_o = `VEC_MODE216;
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mult_sel_subword_o = instr_rdata_i[13:12];
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mult_signed_mode_o = instr_rdata_i[31:30];
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@ -475,184 +495,6 @@ module riscv_decoder
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endcase
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end
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/*
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`OPCODE_ALU: begin // Arithmetic Operation
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rega_used_o = 1'b1;
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regb_used_o = 1'b1;
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case (instr_rdata_i[9:8])
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2'b00: begin // ALU Operation
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regfile_alu_we = 1'b1;
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casex (instr_rdata_i[3:0])
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4'b110X: begin // l.ext{b,h,w}{s,z}
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alu_operator = {3'b010, instr_rdata_i[7:6], instr_rdata_i[0]};
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regb_used_o = 1'b0; // register b is not used
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end
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4'b1111: begin // l.ff1
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alu_operator = `ALU_FF1;
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end
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endcase // casex (instr_rdata_i[3:2])
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end
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2'b01: begin // l.fl1, l.clb, l.cnt
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regfile_alu_we = 1'b1;
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regb_used_o = 1'b0;
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case (instr_rdata_i[3:0])
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4'b1101: alu_operator = `ALU_CNT;
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4'b1110: alu_operator = `ALU_CLB;
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4'b1111: alu_operator = `ALU_FL1;
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default: begin
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// synopsys translate_off
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$display("%t: Illegal ALU instruction received.", $time);
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// synopsys translate_on
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regfile_alu_we = 1'b0; // disable Write Enable for illegal instruction
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illegal_insn_o = 1'b1;
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end
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endcase //~case(instr_rdata_i[3:0])
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end
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2'b10: begin // Min, Max, Abs, Avg
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regfile_alu_we = 1'b1;
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case (instr_rdata_i[3:0])
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4'b0000: alu_operator = `ALU_MIN;
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4'b0001: alu_operator = `ALU_MINU;
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4'b0010: alu_operator = `ALU_MAX;
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4'b0011: alu_operator = `ALU_MAXU;
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4'b0100: alu_operator = `ALU_AVG;
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4'b0101: alu_operator = `ALU_AVGU;
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4'b1000: begin
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regb_used_o = 1'b0;
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alu_operator = `ALU_ABS;
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end
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default: begin
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// synopsys translate_off
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$display("%t: Illegal ALU instruction received.", $time);
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// synopsys translate_on
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regfile_alu_we = 1'b0; // disable Write Enable for illegal instruction
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illegal_insn_o = 1'b1;
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end
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endcase //~case(instr_rdata_i[3:0])
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end
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endcase; // case (instr_rdata_i[9:8])
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end
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`OPCODE_VEC: begin // vectorial alu operations
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rega_used_o = 1'b1;
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regfile_alu_we = 1'b1;
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if (instr_rdata_i[0] == 1'b0) // choose vector size
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vector_mode_o = `VEC_MODE16;
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else
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vector_mode_o = `VEC_MODE8;
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if ((instr_rdata_i[7:6] == 2'b01) || (instr_rdata_i[7:6] == 2'b10)) // replicate scalar 2 or 4 times
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scalar_replication_o = 1'b1;
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if (instr_rdata_i[7:6] == 2'b10) // use immediate as operand b
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begin
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_VEC;
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end
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else
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regb_used_o = 1'b1;
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// now decode the sub opcodes
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case (instr_rdata_i[5:1])
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5'b00000: alu_operator = `ALU_ADD;
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5'b00001: alu_operator = `ALU_SUB;
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5'b00010: alu_operator = `ALU_AVG;
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5'b00011: alu_operator = `ALU_MIN;
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5'b00100: alu_operator = `ALU_MAX;
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5'b00101: alu_operator = `ALU_SRL;
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5'b00110: alu_operator = `ALU_SRA;
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5'b00111: alu_operator = `ALU_SLL;
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5'b01000: begin // lv32.mul
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regfile_alu_waddr_sel_o = 2'b01;
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mult_is_running = 1'b1;
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end
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5'b01001: alu_operator = `ALU_OR;
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5'b01010: alu_operator = `ALU_XOR;
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5'b01011: alu_operator = `ALU_AND;
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5'b01100: begin // lv32.ins
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alu_operator = `ALU_INS;
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scalar_replication_o = 1'b1;
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end
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5'b10000: begin // lv32.abs
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regb_used_o = 1'b0; // abs does not use operand b
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alu_operator = `ALU_ABS;
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end
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5'b10001: begin // lv32.ext
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regb_used_o = 1'b0;
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alu_operator = `ALU_EXT;
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end
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default: begin // unknown instruction encountered
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regfile_alu_we = 1'b0;
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illegal_insn_o = 1'b1;
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// synopsys translate_off
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$display("%t: Unknown vector opcode 0x%h.", $time, instr_rdata_i[5:1]);
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// synopsys translate_on
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end
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endcase // instr_rdata[5:1]
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end
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`OPCODE_VCMP: begin // Vectorial comparisons, i.e. lv32.cmp_*, lv32.all_*, lv32.any_*
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rega_used_o = 1'b1;
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regfile_alu_we = 1'b1;
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if (instr_rdata_i[0] == 1'b0) // choose vector size
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vector_mode_o = `VEC_MODE16;
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else
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vector_mode_o = `VEC_MODE8;
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if ((instr_rdata_i[7:6] == 2'b01) || (instr_rdata_i[7:6] == 2'b10)) // replicate scalar 2 or 4 times
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scalar_replication_o = 1'b1;
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if (instr_rdata_i[7:6] == 2'b10) // use immediate as operand b
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begin
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alu_op_b_mux_sel_o = `OP_B_IMM;
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immediate_mux_sel_o = `IMM_VEC;
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end
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else
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regb_used_o = 1'b1;
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// now decode the sub opcodes for the ALU
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case (instr_rdata_i[3:1])
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3'b000: alu_operator = `ALU_EQ;
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3'b001: alu_operator = `ALU_NE;
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3'b010: alu_operator = `ALU_GTS;
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3'b011: alu_operator = `ALU_GES;
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3'b100: alu_operator = `ALU_LTS;
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3'b101: alu_operator = `ALU_LES;
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default: begin // unknown instruction encountered
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illegal_insn_o = 1'b1;
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// synopsys translate_off
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$display("%t: Unknown vector opcode 0x%h.", $time, instr_rdata_i[5:1]);
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// synopsys translate_on
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end
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endcase //~case(instr_rdata_i[3:1])
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alu_cmp_mode_o = instr_rdata_i[5:4]; // which kind of comparison do we have here, i.e. full, any, all
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if((instr_rdata_i[5:4] == `ALU_CMP_ANY) || (instr_rdata_i[5:4] == `ALU_CMP_ALL))
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set_flag = 1'b1; // set the flag for lv32.all_* and lv32.any_*
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end
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*/
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////////////////////////////////////////////////
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// ____ ____ _____ ____ ___ _ _ //
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@ -208,6 +208,8 @@ endfunction // prettyPrintInstruction
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// Set Lower Than Operations
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`define ALU_SLTS 6'b0011_00
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`define ALU_SLTU 6'b0011_01
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`define ALU_SLETS 6'b0011_10
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`define ALU_SLETU 6'b0011_11
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// Extension Operations
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`define ALU_EXTHS 6'b010_000
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`define ALU_EXTWS 6'b010_001
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