Resolve Questa: Defaulting port to var rather than wire

For packed structs used as input/output port, Questa reports
"Defaulting port 'irqs_i' kind to 'var' rather than 'wire'
due to default compile option setting of -svinputport=relaxed."

The relevant help message says:

```
verror 13314:

vlog Message # 13314:
An input port that is declared with a type but without the 'var' keyword
should default to 'wire' for strict LRM conformance. The default compile
option of -svinputport=relaxed is not LRM compliant, and only defaults
4-state scalar or 4-state single dimension vector types to 'wire'.
Consider using -svinputport=net for strict conformance. See the vlog -help
text for other behaviors available with the -svinputport option.
```

In our code base we can rely on the LRM-compliant handling of this
construct and opt into that using `-svinputport=net`.

Fixes #670

dv/uvm/core_ibex/yaml/rtl_simulation.yaml

@@ -110,6 +110,7 @@
   compile:
     cmd:
       - "qrun -f ibex_dv.f -uvmhome uvm-1.2
+              -svinputport=net
               -access=rw+/. -optimize
               -suppress 2583
               -mfcu -cuname design_cuname