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Cleanup branch signals, remove old signals that were no longer used
This commit is contained in:
Andreas Traber
parent
f5d408d7f4
commit
89fec097fb
5 changed files with 30 additions and 49 deletions
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@ -70,12 +70,10 @@ module riscv_controller
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input logic hwloop_jump_i, // modify pc_mux_sel to select the hwloop addr
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// jump/branch signals
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input logic [1:0] jump_in_ex_i, // jump is being calculated in ALU
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input logic branch_taken_ex_i, // branch taken signal from EX ALU
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input logic [1:0] jump_in_id_i, // jump is being calculated in ALU
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input logic [1:0] jump_in_dec_i, // jump is being calculated in ALU
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input logic branch_decision_i, // branch decision is available in EX stage
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// Exception Controller Signals
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input logic exc_req_i,
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output logic exc_ack_o,
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@ -261,8 +259,7 @@ module riscv_controller
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// decode and execute instructions only if the current conditional
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// branch in the EX stage is either not taken, or there is no
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// conditional branch in the EX stage
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if ((jump_in_ex_i == `BRANCH_COND && ~branch_decision_i) ||
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(jump_in_ex_i != `BRANCH_COND))
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if (~branch_taken_ex_i)
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begin // now analyze the current instruction in the ID stage
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is_decoding_o = 1'b1;
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@ -348,7 +345,7 @@ module riscv_controller
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// TODO: make sure this is not done multiple times in a row!!!
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// maybe with an assertion?
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// handle conditional branches
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if (jump_in_ex_i == `BRANCH_COND && branch_decision_i) begin
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if (branch_taken_ex_i) begin
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// there is a branch in the EX stage that is taken
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pc_mux_sel_o = `PC_BRANCH;
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pc_set_o = 1'b1;
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@ -370,7 +367,7 @@ module riscv_controller
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begin
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halt_if_o = 1'b1;
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if (branch_decision_i) begin
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if (branch_taken_ex_i) begin
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// there is a branch in the EX stage that is taken
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pc_mux_sel_o = `PC_BRANCH;
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pc_set_o = 1'b1;
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@ -575,9 +572,4 @@ module riscv_controller
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assign perf_jr_stall_o = jr_stall_o;
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assign perf_ld_stall_o = load_stall_o;
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// Assertions
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assert property (
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@(posedge clk) (pc_mux_sel_o == `PC_BRANCH) |-> (branch_decision_i !== 1'bx) );
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endmodule // controller
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@ -63,7 +63,7 @@ module riscv_debug_unit
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input logic [31:0] curr_pc_id_i,
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input logic [31:0] branch_pc_i,
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input logic [1:0] jump_in_ex_i,
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input logic branch_in_ex_i,
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input logic branch_taken_i,
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output logic [31:0] npc_o,
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@ -254,7 +254,7 @@ module riscv_debug_unit
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if (stall_core_o && (bp_fsm_cs != StallCore)) begin
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pc_tracking_fsm_ns = IFID;
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if (jump_in_ex_i == `BRANCH_COND) begin
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if (branch_in_ex_i) begin
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if (branch_taken_i)
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pc_tracking_fsm_ns = IFEX;
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else
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33
id_stage.sv
33
id_stage.sv
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@ -51,8 +51,7 @@ module riscv_id_stage
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// Jumps and branches
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output logic [1:0] jump_in_id_o,
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output logic [1:0] jump_in_ex_o,
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output logic branch_in_ex_o,
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input logic branch_decision_i,
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output logic [31:0] jump_target_o,
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@ -63,8 +62,6 @@ module riscv_id_stage
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output logic [1:0] exc_pc_mux_o,
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output logic [4:0] exc_vec_pc_mux_o,
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input logic branch_done_i,
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input logic illegal_c_insn_i,
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input logic is_compressed_i,
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@ -183,6 +180,8 @@ module riscv_id_stage
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logic regb_used_dec;
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logic regc_used_dec;
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logic branch_taken_ex;
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logic [1:0] jump_in_id;
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logic [1:0] jump_in_dec;
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logic misaligned_stall;
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@ -321,6 +320,8 @@ module riscv_id_stage
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// signal to 0 for instructions that are done
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assign clear_instr_valid_o = id_ready_o;
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assign branch_taken_ex = branch_in_ex_o & branch_decision_i;
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///////////////////////////////////////////////
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// _ ___ ___ ___ ___ ____ //
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@ -607,7 +608,7 @@ module riscv_id_stage
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// jump/branches
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.jump_in_dec_o ( jump_in_dec ),
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.jump_in_id_o ( jump_in_id_o ),
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.jump_in_id_o ( jump_in_id ),
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.jump_target_mux_sel_o ( jump_target_mux_sel )
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);
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@ -659,11 +660,9 @@ module riscv_id_stage
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.hwloop_jump_i ( hwloop_jump ),
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// jump/branch control
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.branch_taken_ex_i ( branch_taken_ex ),
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.jump_in_id_i ( jump_in_id ),
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.jump_in_dec_i ( jump_in_dec ),
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.jump_in_id_i ( jump_in_id_o ),
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.jump_in_ex_i ( jump_in_ex_o ),
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.branch_decision_i ( branch_decision_i ),
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// Exception Controller Signals
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.exc_req_i ( exc_req ),
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@ -821,7 +820,7 @@ module riscv_id_stage
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branch_pc_ex_o <= '0;
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end
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else begin
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if (jump_in_id_o == `BRANCH_COND && id_valid_o)
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if (jump_in_id == `BRANCH_COND && id_valid_o)
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branch_pc_ex_o <= current_pc_id_i;
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end
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end
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@ -860,7 +859,7 @@ module riscv_id_stage
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data_misaligned_ex_o <= 1'b0;
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jump_in_ex_o <= `BRANCH_NONE;
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branch_in_ex_o <= 1'b0;
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end
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else if (data_misaligned_i) begin
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@ -917,7 +916,7 @@ module riscv_id_stage
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data_misaligned_ex_o <= 1'b0;
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jump_in_ex_o <= jump_in_id_o;
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branch_in_ex_o <= jump_in_id == `BRANCH_COND;
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end else if(ex_ready_i) begin
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// EX stage is ready but we don't have a new instruction for it,
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// so we set all write enables to 0, but unstall the pipe
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@ -932,7 +931,7 @@ module riscv_id_stage
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data_misaligned_ex_o <= 1'b0;
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jump_in_ex_o <= `BRANCH_NONE;
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branch_in_ex_o <= 1'b0;
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end
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end
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end
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@ -942,4 +941,12 @@ module riscv_id_stage
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assign id_ready_o = (~misaligned_stall) & (~jr_stall) & (~load_stall) & ex_ready_i;
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assign id_valid_o = (~halt_id) & id_ready_o;
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//----------------------------------------------------------------------------
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// Assertions
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//----------------------------------------------------------------------------
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// make sure that branch decision is valid when jumping
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assert property (
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@(posedge clk) (branch_in_ex_o) |-> (branch_decision_i !== 1'bx) );
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endmodule
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@ -70,14 +70,9 @@ module riscv_if_stage
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input logic [1:0] exc_pc_mux_i, // selects ISR address
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input logic [4:0] exc_vec_pc_mux_i, // selects ISR address for vectorized interrupt lines
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output logic branch_done_o, // we already performed a branch
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// jump and branch target and decision
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input logic [1:0] jump_in_id_i,
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input logic [1:0] jump_in_ex_i, // jump in EX -> get PC from jump target (could also be branch)
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input logic [31:0] jump_target_id_i, // jump target address
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input logic [31:0] jump_target_ex_i, // jump target address
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input logic branch_decision_i,
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// from hwloop controller
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input logic hwloop_jump_i,
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@ -421,6 +416,4 @@ module riscv_if_stage
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assign if_ready_o = valid & id_ready_i;
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assign if_valid_o = (~halt_if_i) & if_ready_o;
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assign branch_done_o = branch_req_Q;
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endmodule
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@ -98,8 +98,6 @@ module riscv_core
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logic [1:0] exc_pc_mux_id; // Mux selector for exception PC
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logic [4:0] exc_vec_pc_mux_id; // Mux selector for vectorized IR lines
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logic branch_done; // Branch already done
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logic lsu_load_err;
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logic lsu_store_err;
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@ -111,8 +109,7 @@ module riscv_core
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// Jump and branch target and decision (EX->IF)
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logic [31:0] jump_target_id, jump_target_ex;
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logic [1:0] jump_in_id;
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logic [1:0] jump_in_ex;
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logic branch_in_ex;
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logic branch_decision;
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logic core_busy;
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@ -273,8 +270,6 @@ module riscv_core
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.exc_pc_mux_i ( exc_pc_mux_id ),
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.exc_vec_pc_mux_i ( exc_vec_pc_mux_id ),
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.branch_done_o ( branch_done ),
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// from hwloop controller
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.hwloop_jump_i ( hwloop_jump ),
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.hwloop_target_i ( hwloop_target ), // pc from hwloop start address
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@ -283,10 +278,7 @@ module riscv_core
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.dbg_npc_i ( dbg_npc ),
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.dbg_set_npc_i ( dbg_set_npc ),
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// Jump and branch target and decision
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.jump_in_id_i ( jump_in_id ),
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.jump_in_ex_i ( jump_in_ex ),
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.branch_decision_i ( branch_decision ),
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// Jump targets
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.jump_target_id_i ( jump_target_id ),
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.jump_target_ex_i ( jump_target_ex ),
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@ -327,8 +319,7 @@ module riscv_core
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.instr_req_o ( instr_req_int ),
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// Jumps and branches
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.jump_in_id_o ( jump_in_id ),
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.jump_in_ex_o ( jump_in_ex ),
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.branch_in_ex_o ( branch_in_ex ),
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.branch_decision_i ( branch_decision ),
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.jump_target_o ( jump_target_id ),
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@ -339,8 +330,6 @@ module riscv_core
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.exc_pc_mux_o ( exc_pc_mux_id ),
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.exc_vec_pc_mux_o ( exc_vec_pc_mux_id ),
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.branch_done_i ( branch_done ),
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.illegal_c_insn_i ( illegal_c_insn_id ),
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.is_compressed_i ( is_compressed_id ),
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@ -671,7 +660,7 @@ module riscv_core
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.curr_pc_id_i ( current_pc_id ), // from IF stage
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.branch_pc_i ( branch_pc_ex ), // PC of last executed branch (in EX stage)
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.jump_in_ex_i ( jump_in_ex ),
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.branch_in_ex_i ( branch_in_ex ),
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.branch_taken_i ( branch_decision ),
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.npc_o ( dbg_npc ), // PC from debug unit
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