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Try to fix misaligned

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This commit is contained in:
Markus Wegmann 2017-01-12 17:47:37 +01:00
parent 21f393a96c
commit 8c38f04007
4 changed files with 4 additions and 7 deletions
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2
controller.sv
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@ -420,7 +420,7 @@ module riscv_controller
end else begin
// handle exceptions
if (exc_req_i) begin
if (exc_req_i & id_ready_i) begin
pc_mux_o = PC_EXCEPTION;
pc_set_o = 1'b1;
exc_ack_o = 1'b1;

5
id_stage.sv
View file

@ -224,7 +224,7 @@ module riscv_id_stage
input logic data_misaligned_i,
// CONFIG_REGION: MERGE_ID_EX
`ifdef MERGE_ID_EX
input logic misaligned_addr_i,
input logic [31:0] misaligned_addr_i,
`endif
`endif // ONLY_ALIGNED
@ -816,15 +816,12 @@ module riscv_id_stage
IMMB_I: imm_b = imm_i_type;
IMMB_S: imm_b = imm_s_type;
IMMB_U: imm_b = imm_u_type;
// CONFIG_REGION: NO_JUMP_ADDER
`ifndef NO_JUMP_ADDER
// CONFIG_REGION: ONLY_ALIGNED
`ifndef ONLY_ALIGNED
IMMB_PCINCR: imm_b = (is_compressed_i && (~data_misaligned_i)) ? 32'h2 : 32'h4;
`else
IMMB_PCINCR: imm_b = (is_compressed_i) ? 32'h2 : 32'h4;
`endif // ONLY_ALIGNED
`endif // NO_JUMP_ADDER
IMMB_S2: imm_b = imm_s2_type;
IMMB_BI: imm_b = imm_bi_type;

2
load_store_unit.sv
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@ -75,7 +75,7 @@ module riscv_load_store_unit
output logic data_misaligned_o, // misaligned access was detected -> to controller
// CONFIG_REGION: MERGE_ID_EX
`ifdef MERGE_ID_EX
output logic misaligned_addr_o,
output logic [31:0] misaligned_addr_o,
`endif
`endif // ONLY_ALIGNED

2
riscv_core.sv
View file

@ -131,7 +131,7 @@ module riscv_core
logic data_misaligned;
// CONFIG_REGION: MERGE_ID_EX
`ifdef MERGE_ID_EX
logic misaligned_addr;
logic [31:0] misaligned_addr;
`endif
`endif // ONLY_ALIGNED