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Add reg-reg and post-increment load/stores to tracer
This commit is contained in:
Sven Stucki
parent
9ff25b5a1d
commit
8fa5f6a522
2 changed files with 126 additions and 40 deletions
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@ -128,7 +128,6 @@
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// RV32M
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`define INSTR_MUL { 7'b0000001, 10'b?, 3'b000, 5'b?, `OPCODE_OP }
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/* not implemented
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`define INSTR_MULH { 7'b0000001, 10'b?, 3'b001, 5'b?, `OPCODE_OP }
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`define INSTR_MULHSU { 7'b0000001, 10'b?, 3'b010, 5'b?, `OPCODE_OP }
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`define INSTR_MULHU { 7'b0000001, 10'b?, 3'b011, 5'b?, `OPCODE_OP }
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@ -136,14 +135,9 @@
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`define INSTR_DIVU { 7'b0000001, 10'b?, 3'b101, 5'b?, `OPCODE_OP }
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`define INSTR_REM { 7'b0000001, 10'b?, 3'b110, 5'b?, `OPCODE_OP }
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`define INSTR_REMU { 7'b0000001, 10'b?, 3'b111, 5'b?, `OPCODE_OP }
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*/
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// PULP custom instructions
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// Post-indexed load
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`define INSTR_LBPOST { 17'b?, 3'b011, 5'b?, `OPCODE_LOAD_POST }
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`define INSTR_LHPOST { 17'b?, 3'b110, 5'b?, `OPCODE_LOAD_POST }
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`define INSTR_LWPOST { 17'b?, 3'b111, 5'b?, `OPCODE_LOAD_POST }
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`define INSTR_MAC { 2'b00, 15'b?, 3'b000, 5'b?, `OPCODE_PULP_OP }
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// Source/Destination register instruction index
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`define REG_S1 19:15
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158
riscv_core.sv
158
riscv_core.sv
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@ -648,16 +648,25 @@ module riscv_core
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// Execution trace generation
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// synopsys translate_off
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`ifdef TRACE_EXECUTION
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integer f;
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string fn;
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integer f;
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string fn;
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integer cycles;
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logic [31:0] instr;
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logic compressed;
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logic [31:0] pc;
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logic [4:0] rd, rs1, rs2;
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logic [31:0] rs1_value, rs2_value;
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logic [4:0] rd, rs1, rs2, rs3;
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logic [31:0] rs1_value, rs2_value, rs3_value;
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logic [31:0] imm;
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string mnemonic;
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string mnemonic;
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// cycle counter
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0)
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cycles = 0;
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else
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cycles = cycles + 1;
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end
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// open/close output file for writing
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initial
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@ -688,6 +697,8 @@ module riscv_core
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rs1_value = id_stage_i.operand_a_fw_id;
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rs2 = instr[`REG_S2];
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rs2_value = id_stage_i.operand_b_fw_id;
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rs3 = instr[`REG_S3];
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rs3_value = id_stage_i.alu_operand_c;
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// special case for WFI because we don't wait for unstalling there
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if ((id_valid && is_decoding) || id_stage_i.controller_i.pipe_flush_i)
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@ -719,15 +730,6 @@ module riscv_core
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`INSTR_BGE: printSBInstr("BGE");
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`INSTR_BLTU: printSBInstr("BLTU");
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`INSTR_BGEU: printSBInstr("BGEU");
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// LOAD
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`INSTR_LB: printILInstr("LB");
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`INSTR_LBPOST: printILInstr("LBPOST");
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`INSTR_LH: printILInstr("LH");
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`INSTR_LHPOST: printILInstr("LHPOST");
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`INSTR_LW: printILInstr("LW");
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`INSTR_LWPOST: printILInstr("LWPOST");
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`INSTR_LBU: printILInstr("LBU");
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`INSTR_LHU: printILInstr("LHU");
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// STORE
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`INSTR_SB: printSInstr("SB");
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`INSTR_SH: printSInstr("SH");
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@ -776,11 +778,20 @@ module riscv_core
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`INSTR_RDINSTRETH: printRDInstr("RDINSTRETH");
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// RV32M
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`INSTR_MUL: printRInstr("MUL");
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/*
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`INSTR_MULH: printRInstr("MULH");
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`INSTR_MULHSU: printRInstr("MULHSU");
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`INSTR_MULHU: printRInstr("MULHU");
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*/
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`INSTR_DIV: printRInstr("DIV");
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`INSTR_DIVU: printRInstr("DIVU");
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`INSTR_REM: printRInstr("REM");
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`INSTR_REMU: printRInstr("REMU");
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// PULP specific
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`INSTR_MAC: printR3Instr("MAC");
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// opcodes with custom decoding
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{25'b?, `OPCODE_LOAD}: printLoadInstr();
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{25'b?, `OPCODE_LOAD_POST}: printLoadInstr();
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{25'b?, `OPCODE_STORE}: printStoreInstr();
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{25'b?, `OPCODE_STORE_POST}: printStoreInstr();
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default: printMnemonic("INVALID");
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endcase // unique case (instr)
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@ -788,14 +799,6 @@ module riscv_core
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end
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end // always @ (posedge clk)
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0)
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cycles = 0;
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else
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cycles = cycles + 1;
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end
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function void printMnemonic(input string mnemonic);
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begin
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riscv_core.mnemonic = mnemonic;
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@ -819,6 +822,14 @@ module riscv_core
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end
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endfunction // printRInstr
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function void printR3Instr(input string mnemonic);
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begin
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riscv_core.mnemonic = mnemonic;
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$fdisplay(f, "%7s\tx%0d, x%0d (0x%h), x%0d (0x%h), x%0d (0x%h)", mnemonic,
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rd, rs1, rs1_value, rs2, rs2_value, rs3, rs3_value);
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end
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endfunction // printRInstr
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function void printIInstr(input string mnemonic);
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begin
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riscv_core.mnemonic = mnemonic;
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@ -828,15 +839,6 @@ module riscv_core
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end
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endfunction // printIInstr
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function void printILInstr(input string mnemonic);
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begin
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riscv_core.mnemonic = mnemonic;
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imm = id_stage_i.imm_i_type;
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$fdisplay(f, "%7s\tx%0d, x%0d (0x%h), 0x%0h (imm) (-> 0x%h)", mnemonic,
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rd, rs1, rs1_value, imm, imm+rs1_value);
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end
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endfunction // printILInstr
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function void printSInstr(input string mnemonic);
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begin
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riscv_core.mnemonic = mnemonic;
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@ -886,6 +888,96 @@ module riscv_core
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end
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endfunction // printCSRInstr
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function void printLoadInstr();
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string mnemonic;
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logic [2:0] size;
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begin
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// detect reg-reg load and find size
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size = instr[14:12];
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if (instr[14:12] == 3'b111)
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size = instr[30:28];
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case (size)
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3'b000: mnemonic = "LB";
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3'b001: mnemonic = "LH";
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3'b010: mnemonic = "LW";
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3'b100: mnemonic = "LBU";
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3'b101: mnemonic = "LHU";
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3'b011,
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3'b110,
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3'b111: begin
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printMnemonic("INVALID");
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return;
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end
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endcase
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// compose mnemonic
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if (instr[14:12] == 3'b111)
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mnemonic = {mnemonic, "RR"};
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if (instr[6:0] == `OPCODE_LOAD_POST)
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mnemonic = {mnemonic, "POST"};
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riscv_core.mnemonic = mnemonic;
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if (instr[14:12] != 3'b111) begin
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// regular load
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imm = id_stage_i.imm_i_type;
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if (instr[6:0] != `OPCODE_LOAD_POST)
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$fdisplay(f, "%7s\tx%0d, x%0d (0x%h), 0x%0h (imm) (-> 0x%h)",
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mnemonic, rd, rs1, rs1_value, imm, imm+rs1_value);
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else
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$fdisplay(f, "%7s\tx%0d, x%0d! (0x%h), 0x%0h (imm) (-> 0x%h)",
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mnemonic, rd, rs1, rs1_value, imm, rs1_value);
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end else begin
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// reg-reg load
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if (instr[6:0] != `OPCODE_LOAD_POST)
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$fdisplay(f, "%7s\tx%0d, x%0d (0x%h), x%0d (0x%h) (-> 0x%h)", mnemonic,
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rd, rs1, rs1_value, rs2, rs2_value, rs1_value+rs2_value);
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else
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$fdisplay(f, "%7s\tx%0d, x%0d! (0x%h), x%0d (0x%h) (-> 0x%h)", mnemonic,
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rd, rs1, rs1_value, rs2, rs2_value, rs1_value);
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end
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end
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endfunction
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function void printStoreInstr();
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string mnemonic;
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begin
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case (instr[13:12])
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2'b00: mnemonic = "SB";
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2'b01: mnemonic = "SH";
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2'b10: mnemonic = "SW";
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2'b11: begin
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printMnemonic("INVALID");
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return;
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end
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endcase
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// compose mnemonic
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if (instr[14])
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mnemonic = {mnemonic, "RR"};
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if (instr[6:0] == `OPCODE_STORE_POST)
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mnemonic = {mnemonic, "POST"};
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riscv_core.mnemonic = mnemonic;
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if (instr[14] == 1'b0) begin
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// regular store
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imm = id_stage_i.imm_s_type;
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if (instr[6:0] != `OPCODE_STORE_POST)
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$fdisplay(f, "%7s\tx%0d (0x%h), x%0d (0x%h), 0x%0h (imm) (-> 0x%h)",
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mnemonic, rs1, rs1_value, rs2, rs2_value, imm, imm+rs1_value);
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else
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$fdisplay(f, "%7s\tx%0d! (0x%h), x%0d (0x%h), 0x%0h (imm) (-> 0x%h)",
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mnemonic, rs1, rs1_value, rs2, rs2_value, imm, rs1_value);
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end else begin
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// reg-reg store
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if (instr[6:0] != `OPCODE_STORE_POST)
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$fdisplay(f, "%7s\tx%0d (0x%h), x%0d (0x%h), x%0d (0x%h) (-> 0x%h)", mnemonic,
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rs1, rs1_value, rs2, rs2_value, rs3, rs3_value, rs1_value+rs3_value);
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else
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$fdisplay(f, "%7s\tx%0d! (0x%h), x%0d (0x%h), x%0d (0x%h) (-> 0x%h)", mnemonic,
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rs1, rs1_value, rs2, rs2_value, rs3, rs3_value, rs1_value);
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end
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end
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endfunction // printSInstr
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`endif // TRACE_EXECUTION
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// synopsys translate_on
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`endif
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