Add common register file module to build targets

dv/uvm/core_ibex/ibex_dv.f

@@ -97,6 +97,7 @@ ${PRJ_DIR}/rtl/ibex_multdiv_slow.sv
 ${PRJ_DIR}/rtl/ibex_multdiv_fast.sv
 ${PRJ_DIR}/rtl/ibex_prefetch_buffer.sv
 ${PRJ_DIR}/rtl/ibex_fetch_fifo.sv
+${PRJ_DIR}/rtl/ibex_register_file_common.sv
 ${PRJ_DIR}/rtl/ibex_register_file_ff.sv
 ${PRJ_DIR}/rtl/ibex_register_file_fpga.sv
 ${PRJ_DIR}/rtl/ibex_register_file_latch.sv

ibex_top.core

@@ -19,6 +19,7 @@ filesets:
       - lowrisc:prim:onehot_check
       - lowrisc:prim:onehot
     files:
+      - rtl/ibex_register_file_common.sv
       - rtl/ibex_register_file_ff.sv # generic FF-based
       - rtl/ibex_register_file_fpga.sv # FPGA
       - rtl/ibex_register_file_latch.sv # ASIC

rtl/ibex_core.f

@@ -17,5 +17,6 @@ ibex_multdiv_slow.sv
 ibex_multdiv_fast.sv
 ibex_prefetch_buffer.sv
 ibex_fetch_fifo.sv
+ibex_register_file_common.sv
 ibex_register_file_ff.sv
 ibex_core.sv