Consolidate some debug generation options, and make the signature_addr handshake optional (#253)

dv/uvm/Makefile

@@ -41,10 +41,8 @@ SIGNATURE_ADDR      := 8ffffffc
 PASS_VAL            := 0x1
 # Value written to SIGNATURE_ADDR that indicates test failure
 FAIL_VAL            := 0x0
-# Value written to SIGNATURE_ADDR to indicate that debug stimulus can safely be sent
-DEBUG_START_REQ     := 2
-# Value written to SIGNATURE_ADDR to indicate that interrupt stimulus can safely be sent
-IRQ_START_REQ       := 3
+# Value written to SIGNATURE_ADDR to indicate that stimulus can safely be sent from testbench
+CORE_START_REQ     := 2
 
 SHELL=/bin/bash
 
@@ -87,8 +85,7 @@ CSR_OPTS=--csr_yaml=${CSR_FILE} \
        +define+RISCV_DV_EXT_FILE_LIST=${DV_DIR}/riscv_dv_extension/flist \
        +incdir+${DV_DIR}/riscv_dv_extension/ " \
      --sim_opts="+uvm_set_type_override=riscv_asm_program_gen,ibex_asm_program_gen \
-                 +signature_addr=${SIGNATURE_ADDR} +debug_start_req=${DEBUG_START_REQ} \
-								 +irq_start_req=${IRQ_START_REQ}";
+                 +signature_addr=${SIGNATURE_ADDR}";
 
 # Compile the generated assmebly programs to ELF/BIN
 gcc_compile:
@@ -133,7 +130,7 @@ rtl_sim:
      --en_cov ${COV} \
      --en_wave ${WAVES} \
      --sim_opts="+signature_addr=0x${SIGNATURE_ADDR} +pass_val=${PASS_VAL} +fail_val=${FAIL_VAL} \
-                 +debug_start_req=0x${DEBUG_START_REQ} +irq_start_req=0x${IRQ_START_REQ}" \
+                 +core_start_req=0x${CORE_START_REQ}" \
      ${SIM_OPTS}
 
 # Compare the regression result between ISS and RTL sim

dv/uvm/env/core_ibex_env_cfg.sv

@@ -6,30 +6,30 @@ class core_ibex_env_cfg extends uvm_object;
 
   bit       enable_irq_seq;
   bit       enable_debug_seq;
+  bit       require_signature_addr;
   bit[31:0] pass_val, fail_val;
   bit[31:0] signature_addr;
-  bit[31:0] debug_start_req;
-  bit[31:0] irq_start_req;
+  bit[31:0] core_start_req;
 
   `uvm_object_utils_begin(core_ibex_env_cfg)
     `uvm_field_int(enable_irq_seq,   UVM_DEFAULT)
     `uvm_field_int(enable_debug_seq, UVM_DEFAULT)
+    `uvm_field_int(require_signature_addr, UVM_DEFAULT)
     `uvm_field_int(pass_val, UVM_DEFAULT)
     `uvm_field_int(fail_val, UVM_DEFAULT)
     `uvm_field_int(signature_addr, UVM_DEFAULT)
-    `uvm_field_int(debug_start_req, UVM_DEFAULT)
-    `uvm_field_int(irq_start_req, UVM_DEFAULT)
+    `uvm_field_int(core_start_req, UVM_DEFAULT)
   `uvm_object_utils_end
 
   function new(string name = "");
     super.new(name);
     void'($value$plusargs("enable_irq_seq=%0d", enable_irq_seq));
     void'($value$plusargs("enable_debug_seq=%0d", enable_debug_seq));
+    void'($value$plusargs("require_signature_addr=%0d", require_signature_addr));
     void'($value$plusargs("pass_val=%0h", pass_val));
     void'($value$plusargs("fail_val=%0h", fail_val));
     void'($value$plusargs("signature_addr=%0h", signature_addr));
-    void'($value$plusargs("debug_start_req=%0h", debug_start_req));
-    void'($value$plusargs("irq_start_req=%0h", irq_start_req));
+    void'($value$plusargs("core_start_req=%0h", core_start_req));
   endfunction
 
 endclass

dv/uvm/riscv_dv_extension/testlist.yaml

@@ -6,7 +6,6 @@
   description: >
     Arithmetic instruction test, no load/store/branch instructions
   gen_opts: >
-    +empty_debug_section=1
     +instr_cnt=10000
     +num_of_sub_program=0
     +no_fence=1
@@ -23,7 +22,6 @@
   iterations: 10
   gen_test: riscv_instr_base_test
   gen_opts: >
-    +empty_debug_section=1
     +instr_cnt=10000
     +num_of_sub_program=5
     +boot_mode=m
@@ -35,7 +33,6 @@
   iterations: 10
   gen_test: riscv_instr_base_test
   gen_opts: >
-    +empty_debug_section=1
     +instr_cnt=10000
     +num_of_sub_program=5
     +directed_instr_0=riscv_load_store_rand_instr_stream,4
@@ -52,7 +49,6 @@
   iterations: 10
   gen_test: riscv_instr_base_test
   gen_opts: >
-    +empty_debug_section=1
     +instr_cnt=15000
     +num_of_sub_program=20
     +directed_instr_0=riscv_load_store_rand_instr_stream,8
@@ -65,7 +61,6 @@
   iterations: 10
   gen_test: riscv_instr_base_test
   gen_opts: >
-    +empty_debug_section=1
     +instr_cnt=10000
     +num_of_sub_program=5
     +directed_instr_0=riscv_load_store_rand_instr_stream,40
@@ -83,7 +78,6 @@
   iterations: 10
   gen_test: riscv_rand_instr_test
   gen_opts: >
-    +empty_debug_section=1
     +enable_illegal_instruction=1
   rtl_test: core_ibex_base_test
 
@@ -94,7 +88,6 @@
   iterations: 10
   gen_test: riscv_rand_instr_test
   gen_opts: >
-    +empty_debug_section=1
     +enable_hint_instruction=1
   rtl_test: core_ibex_base_test
 
@@ -105,7 +98,6 @@
   iterations: 10
   gen_test: riscv_rand_instr_test
   gen_opts: >
-    +empty_debug_section=1
     +instr_cnt=6000
     +no_ebreak=0
   rtl_test: core_ibex_base_test
@@ -116,6 +108,8 @@
   iterations: 10
   gen_test: riscv_instr_base_test
   gen_opts: >
+    +require_signature_addr=1
+    +gen_debug_section=1
     +no_ebreak=1
     +no_branch_jump=1
     +instr_cnt=6000
@@ -124,11 +118,30 @@
     +num_of_sub_program=0
   rtl_test: core_ibex_debug_test
   sim_opts: >
+    +require_signature_addr=1
     +enable_debug_seq=1
   compare_opts:
     compare_final_value_only: 1
     verbose: 1
 
+- test: riscv_debug_stress_test
+  description: >
+    Randomly assert debug_req_i more often, debug_rom is empty, with only a dret instruction
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +require_signature_addr=1
+    +no_ebreak=1
+    +instr_cnt=6000
+    +no_csr_instr=1
+    +no_fence=1
+  rtl_test: core_ibex_debug_test
+  sim_opts: >
+    +frequent_debug=1
+    +require_signature_addr=1
+  compare_opts:
+    compare_final_value_only : 1
+    verbose: 1
+
 - test: riscv_debug_branch_jump_test
   description: >
     Randomly assert debug_req_i, insert branch instructions and subprograms into debug_rom to make core
@@ -136,14 +149,17 @@
   iterations: 10
   gen_test: riscv_rand_instr_test
   gen_opts: >
+    +require_signature_addr=1
+    +gen_debug_section=1
     +no_ebreak=1
-    +instr_cnt=10000
+    +instr_cnt=6000
     +no_csr_instr=1
     +no_fence=1
     +num_of_sub_program=5
-    +num_debug_sub_program=2
+    +num_debug_sub_program=5
   rtl_test: core_ibex_debug_test
   sim_opts: >
+    +require_signature_addr=1
     +enable_debug_seq=1
   compare_opts:
     compare_final_value_only: 1
@@ -156,10 +172,12 @@
   iterations: 0
   gen_test: riscv_rand_instr_test
   gen_opts: >
+    +require_signature_addr=1
     +instr_cnt=6000
     +no_ebreak=0
   rtl_test: core_ibex_base_test
   sim_opts: >
+    +require_signature_addr=1
     +enable_debug_seq=1
   compare_opts:
     compare_final_value_only: 1
@@ -174,11 +192,12 @@
   iterations: 2
   gen_test: riscv_rand_instr_test
   gen_opts: >
-    +empty_debug_section=1
+    +require_signature_addr=1
     +skip_trap_handling=1
     +no_wfi=0
   rtl_test: core_ibex_base_test
   sim_opts: >
+    +require_signature_addr=1
     +enable_irq_seq=1
   compare_opts:
     compare_final_value_only: 1
@@ -188,8 +207,11 @@
     Random instruction test with complete interrupt handling
   iterations: 0
   gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +require_signature_addr=1
   rtl_test: core_ibex_base_test
   sim_opts: >
+    +require_signature_addr=1
     +enable_irq_seq=1
   compare_opts:
     compare_final_value_only: 1
@@ -208,7 +230,6 @@
   iterations: 5
   gen_test: riscv_instr_base_test
   gen_opts: >
-    +empty_debug_section=1
     +instr_cnt=10000
     +num_of_sub_program=5
     +directed_instr_0=riscv_load_store_rand_instr_stream,20

dv/uvm/tests/core_ibex_base_test.sv

@@ -15,6 +15,10 @@ class core_ibex_base_test extends uvm_test;
   bit                                             enable_debug_seq;
   irq_seq                                         irq_seq_h;
   int unsigned                                    timeout_in_cycles = 2000000;
+  // If no signature_addr handshake functionality is desired between the
+  // testbench and the generated code, the test will wait for the specified
+  // number of cycles before starting stimulus sequences (irq and debug)
+  int unsigned                                    stimulus_delay = 800;
   uvm_tlm_analysis_fifo #(ibex_mem_intf_seq_item) addr_ph_port;
 
   `uvm_component_utils(core_ibex_base_test)

dv/uvm/tests/core_ibex_test_lib.sv

@@ -37,8 +37,7 @@ endclass
 // Debug test class
 class core_ibex_debug_test extends core_ibex_base_test;
 
-  bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] irq_data;
-  bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] debug_data;
+  bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] core_start_data;
 
   `uvm_component_utils(core_ibex_debug_test)
   `uvm_component_new
@@ -51,13 +50,22 @@ class core_ibex_debug_test extends core_ibex_base_test;
     dut_vif.fetch_enable = 1'b1;
     fork
       vseq.start(env.vseqr);
-      if (cfg.enable_irq_seq) begin
-        wait_for_mem_txn(cfg.signature_addr, cfg.irq_start_req, irq_data);
-        vseq.start_irq_seq();
-      end
-      if (cfg.enable_debug_seq) begin
-        wait_for_mem_txn(cfg.signature_addr, cfg.debug_start_req, debug_data);
-        vseq.start_debug_seq();
+      begin
+        if (cfg.require_signature_addr) begin
+          wait_for_mem_txn(cfg.signature_addr, cfg.core_start_req, core_start_data);
+        end else begin
+          // If no signature_addr functionality is desired, then the test will
+          // simply wait for an adequate number of cycles
+          clk_vif.wait_clks(stimulus_delay);
+        end
+        fork
+          if (cfg.enable_irq_seq) begin
+            vseq.start_irq_seq();
+          end
+          if (cfg.enable_debug_seq) begin
+            vseq.start_debug_seq();
+          end
+        join_none
       end
     join_none
     wait_for_test_done();