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[ibex/dv] Modify EOT ecall check

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This PR slightly modifies how we wait for the end of an Ibex sim.
Currently we wait on dut_vif.dut_cb.ecall, which will be delayed by a
cycle as it is in a clocking block.
However we should end the test immediately when an ecall is seen, so we
should rather wait on dut_vif.ecall instead to be more accurate and
prevent potential race conditions caused by irq/debug stimulus being
sent on the same cycle as an ecall instruction is executed by the core.

Signed-off-by: Udi Jonnalagadda <udij@google.com>
This commit is contained in:
Udi Jonnalagadda 2020-11-06 17:43:16 -08:00 • committed by Tom Roberts
parent 6fb378c40c
commit 94c87ba987
1 changed files with 1 additions and 1 deletions
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2
dv/uvm/core_ibex/tests/core_ibex_base_test.sv
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@ -122,7 +122,7 @@ class core_ibex_base_test extends uvm_test;
virtual task wait_for_test_done();
fork
begin
wait (dut_vif.dut_cb.ecall === 1'b1);
wait (dut_vif.ecall === 1'b1);
vseq.stop();
`uvm_info(`gfn, "ECALL instruction is detected, test done", UVM_LOW)
// De-assert fetch enable to finish the test