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[fcov] Add missing security related coverpoints

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Also introduces using `DV_FCOV_EXPR_SEEN for some existing coverpoints
where appropriate.
This commit is contained in:
Greg Chadwick 2022-11-16 16:24:35 +00:00 • committed by Greg Chadwick
parent eeede2d98b
commit 957349e9a7
1 changed files with 19 additions and 7 deletions
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26
dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
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@ -18,7 +18,9 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
input fcov_csr_write,
input fcov_rf_ecc_err_a_id,
input fcov_rf_ecc_err_b_id
input fcov_rf_ecc_err_b_id,
input ibex_mubi_t fetch_enable_i
);
`include "dv_fcov_macros.svh"
import uvm_pkg::*;
@ -452,13 +454,23 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
cp_dummy_instr_id_stage: coverpoint if_stage_i.dummy_instr_id_o;
cp_dummy_instr_wb_stage: coverpoint wb_stage_i.dummy_instr_wb_o;
cp_rf_a_ecc_err: coverpoint fcov_rf_ecc_err_a_id;
cp_rf_b_ecc_err: coverpoint fcov_rf_ecc_err_b_id;
`DV_FCOV_EXPR_SEEN(rf_a_ecc_err, fcov_rf_ecc_err_a_id)
`DV_FCOV_EXPR_SEEN(rf_b_ecc_err, fcov_rf_ecc_err_b_id)
cp_icache_ecc_err : coverpoint if_stage_i.icache_ecc_error_o;
`DV_FCOV_EXPR_SEEN(icache_ecc_err, if_stage_i.icache_ecc_error_o)
cp_lockstep_err : coverpoint lockstep_glitch_err;
cp_rf_we_glitch_err : coverpoint rf_we_glitch_err;
`DV_FCOV_EXPR_SEEN(mem_load_ecc_err, load_store_unit_i.load_resp_intg_err_o)
`DV_FCOV_EXPR_SEEN(mem_store_ecc_err, load_store_unit_i.store_resp_intg_err_o)
`DV_FCOV_EXPR_SEEN(lockstep_err, lockstep_glitch_err)
`DV_FCOV_EXPR_SEEN(rf_we_glitch_err, rf_we_glitch_err)
`DV_FCOV_EXPR_SEEN(pc_mismatch_err, if_stage_i.pc_mismatch_alert_o)
cp_fetch_enable: coverpoint fetch_enable_i {
bins fetch_on = {IbexMuBiOn};
bins fetch_off = {IbexMuBiOff};
bins fetch_inval = default;
}
// TODO: MRET/WFI in debug mode?
// Specific cover points for these as `id_instr_category` will be InstrCategoryPrivIllegal when
@ -729,7 +741,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
dummy_instr_config_cross: cross cp_dummy_instr_type, cp_dummy_instr_mask
iff (cs_registers_i.dummy_instr_en_o);
rf_ecc_err_cross: cross cp_rf_a_ecc_err, cp_rf_b_ecc_err
rf_ecc_err_cross: cross fcov_rf_ecc_err_a_id, fcov_rf_ecc_err_b_id
iff (id_stage_i.instr_valid_i);
// Each stage sees a debug request while executing a dummy instruction.