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[cosim] Fix various CSR mismatches

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This sets the initial values of a few CSRs in spike to match Ibex. It
also adds an mcause fixup so we get WARL behaviour matching Ibex.
This commit is contained in:
Greg Chadwick 2022-08-13 21:11:14 +01:00 • committed by Greg Chadwick
parent 080ad8df96
commit 95e0947e77
2 changed files with 45 additions and 9 deletions
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39
dv/cosim/spike_cosim.cc
View file

@ -57,9 +57,7 @@ SpikeCosim::SpikeCosim(const std::string &isa_string, uint32_t start_pc,
processor->set_pmp_granularity(1 << (pmp_granularity + 2));
processor->set_ibex_flags(secure_ibex, icache_en);
processor->set_mmu_capability(IMPL_MMU_SBARE);
processor->get_state()->pc = start_pc;
processor->get_state()->mtvec->write(start_mtvec);
initial_proc_setup(start_pc, start_mtvec);
if (log) {
processor->set_debug(true);
@ -440,6 +438,21 @@ void SpikeCosim::leave_nmi_mode() {
#endif
}
void SpikeCosim::initial_proc_setup(uint32_t start_pc, uint32_t start_mtvec) {
processor->get_state()->pc = start_pc;
processor->get_state()->mtvec->write(start_mtvec);
processor->get_state()->csrmap[CSR_MARCHID] =
std::make_shared<const_csr_t>(processor.get(), CSR_MARCHID, IBEX_MARCHID);
processor->set_mmu_capability(IMPL_MMU_SBARE);
for (int i = 0; i < processor->TM.count(); ++i) {
processor->TM.tdata2_write(processor.get(), i, 0);
processor->TM.tdata1_write(processor.get(), i, 0x28001048);
}
}
void SpikeCosim::set_mip(uint32_t mip) {
processor->get_state()->mip->write_with_mask(0xffffffff, mip);
}
@ -521,7 +534,7 @@ void SpikeCosim::clear_errors() { errors.clear(); }
void SpikeCosim::fixup_csr(int csr_num, uint32_t csr_val) {
switch (csr_num) {
case CSR_MSTATUS:
case CSR_MSTATUS: {
reg_t mask =
MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_MPRV | MSTATUS_MPP | MSTATUS_TW;
@ -532,6 +545,24 @@ void SpikeCosim::fixup_csr(int csr_num, uint32_t csr_val) {
processor->put_csr(csr_num, new_val);
#endif
break;
}
case CSR_MCAUSE: {
uint32_t any_interrupt = csr_val & 0x80000000;
uint32_t int_interrupt = csr_val & 0x40000000;
reg_t new_val = (csr_val & 0x0000001f) | any_interrupt;
if (any_interrupt && int_interrupt) {
new_val |= 0x7fffffe0;
}
#ifdef OLD_SPIKE
processor->set_csr(csr_num, new_val);
#else
processor->put_csr(csr_num, new_val);
#endif
break;
}
}
}

15
dv/cosim/spike_cosim.h
View file

@ -5,17 +5,20 @@
#ifndef SPIKE_COSIM_H_
#define SPIKE_COSIM_H_
#include <stdint.h>
#include <deque>
#include <memory>
#include <string>
#include <vector>
#include "cosim.h"
#include "riscv/devices.h"
#include "riscv/log_file.h"
#include "riscv/processor.h"
#include "riscv/simif.h"
#include <stdint.h>
#include <deque>
#include <memory>
#include <string>
#include <vector>
#define IBEX_MARCHID 22
class SpikeCosim : public simif_t, public Cosim {
private:
@ -66,6 +69,8 @@ class SpikeCosim : public simif_t, public Cosim {
void leave_nmi_mode();
void initial_proc_setup(uint32_t start_pc, uint32_t start_mtvec);
int insn_cnt;
public: