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https://github.com/lowRISC/ibex.git
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Move unalignment selection into prefetch buffer
This commit is contained in:
Andreas Traber
parent
5de1132e47
commit
965be8059a
3 changed files with 57 additions and 57 deletions
38
if_stage.sv
38
if_stage.sv
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@ -111,9 +111,6 @@ module riscv_if_stage
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logic [31:0] fetch_rdata;
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logic [31:0] fetch_addr;
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logic fetch_unaligned_valid;
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logic [31:0] fetch_unaligned_rdata;
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logic [31:0] instr_rdata_int;
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@ -129,7 +126,6 @@ module riscv_if_stage
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if (unaligned) begin
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current_pc_if_o = {fetch_addr[31:2], 2'b10};
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instr_rdata_int = fetch_unaligned_rdata;
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end
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end
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@ -195,14 +191,12 @@ module riscv_if_stage
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.branch_i ( branch_req ),
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.addr_i ( {fetch_addr_n[31:2], 2'b00} ),
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.unaligned_i ( unaligned ), // is the current address unaligned?
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.ready_i ( fetch_ready ),
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.valid_o ( fetch_valid ),
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.rdata_o ( fetch_rdata ),
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.addr_o ( fetch_addr ),
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.unaligned_valid_o ( fetch_unaligned_valid ),
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.unaligned_rdata_o ( fetch_unaligned_rdata ),
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// goes to instruction memory / instruction cache
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.instr_req_o ( instr_req_o ),
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.instr_addr_o ( instr_addr_o ),
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@ -224,14 +218,12 @@ module riscv_if_stage
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.branch_i ( branch_req ),
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.addr_i ( {fetch_addr_n[31:2], 2'b00} ),
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.unaligned_i ( unaligned ), // is the current address unaligned?
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.ready_i ( fetch_ready ),
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.valid_o ( fetch_valid ),
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.rdata_o ( fetch_rdata ),
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.addr_o ( fetch_addr ),
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.unaligned_valid_o ( fetch_unaligned_valid ),
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.unaligned_rdata_o ( fetch_unaligned_rdata ),
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// goes to instruction memory / instruction cache
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.instr_req_o ( instr_req_o ),
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.instr_addr_o ( instr_addr_o ),
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@ -304,26 +296,16 @@ module riscv_if_stage
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unaligned = 1'b1;
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if (fetch_valid) begin
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if (is_compressed[1]) begin
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valid = 1'b1; // an instruction is ready for ID stage
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valid = 1'b1; // an instruction is ready for ID stage
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if (req_i && if_valid_o) begin
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// next instruction will be aligned
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fetch_ready = 1'b1;
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if (req_i && if_valid_o) begin
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// next instruction will be aligned
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fetch_ready = 1'b1;
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if (is_compressed[1])
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offset_fsm_ns = WAIT_ALIGNED;
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end
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end else begin
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// not compressed, we are looking at a 32 bit instruction
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if (fetch_unaligned_valid) begin
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valid = 1'b1; // an instruction is ready for ID stage
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if (req_i && if_valid_o) begin
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// next instruction will be unaligned
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fetch_ready = 1'b1;
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offset_fsm_ns = WAIT_UNALIGNED;
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end
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end
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else
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offset_fsm_ns = WAIT_UNALIGNED;
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end
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end
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end
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@ -40,8 +40,7 @@ module riscv_prefetch_L0_buffer
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output logic [31:0] rdata_o,
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output logic [31:0] addr_o,
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output logic unaligned_valid_o,
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output logic [31:0] unaligned_rdata_o,
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input logic unaligned_i,
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// goes to instruction memory / instruction cache
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output logic instr_req_o,
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@ -67,6 +66,10 @@ module riscv_prefetch_L0_buffer
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logic ready_L0;
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logic is_prefetch_q, is_prefetch_n;
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// prepared data for output
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logic [31:0] rdata, unaligned_rdata;
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logic valid, unaligned_valid;
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assign busy_o = (CS != EMPTY && CS != VALID_L0) || instr_req_o;
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@ -112,7 +115,7 @@ module riscv_prefetch_L0_buffer
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always_comb
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begin
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valid_o = 1'b0;
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valid = 1'b0;
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valid_L0 = 1'b0;
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pointer_ns = pointer_cs;
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instr_req_o = 1'b0;
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@ -165,7 +168,7 @@ module riscv_prefetch_L0_buffer
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end
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else // else (branch_i)
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begin
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valid_o = instr_rvalid_i;
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valid = instr_rvalid_i;
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// prepare address even if we don't need it
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// this removes the dependency for instr_addr_o on instr_rvalid_i
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@ -206,7 +209,7 @@ module riscv_prefetch_L0_buffer
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VALID_L0:
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begin
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valid_o = 1'b1;
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valid = 1'b1;
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valid_L0 = 1'b1;
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if (branch_i)
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@ -308,41 +311,41 @@ module riscv_prefetch_L0_buffer
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begin
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if (is_prefetch_q)
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begin
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rdata_o = previous_chunk;
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rdata = previous_chunk;
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addr_o = { last_address[31:4], 2'b11, 2'b00 };
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end
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else
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begin
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if (valid_L0) begin
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rdata_o = L0_buffer[pointer_cs];
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rdata = L0_buffer[pointer_cs];
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addr_o = { current_address[31:4], pointer_cs, 2'b00 };
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end
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else
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begin
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rdata_o = instr_rdata_i[pointer_cs];
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rdata = instr_rdata_i[pointer_cs];
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addr_o = { current_address[31:4], pointer_cs, 2'b00 };
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end
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end
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end
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// the lower part of unaligned_rdata_o is always the higher part of rdata_o
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assign unaligned_rdata_o[15:0] = rdata_o[31:16];
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// the lower part of unaligned_rdata is always the higher part of rdata
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assign unaligned_rdata[15:0] = rdata[31:16];
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always_comb
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begin
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if (valid_L0) begin
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case(addr_o[3:2])
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2'b00: begin unaligned_rdata_o[31:16] = L0_buffer[1][15:0]; unaligned_valid_o = 1'b1; end
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2'b01: begin unaligned_rdata_o[31:16] = L0_buffer[2][15:0]; unaligned_valid_o = 1'b1; end
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2'b10: begin unaligned_rdata_o[31:16] = L0_buffer[3][15:0]; unaligned_valid_o = 1'b1; end
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2'b00: begin unaligned_rdata[31:16] = L0_buffer[1][15:0]; unaligned_valid = 1'b1; end
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2'b01: begin unaligned_rdata[31:16] = L0_buffer[2][15:0]; unaligned_valid = 1'b1; end
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2'b10: begin unaligned_rdata[31:16] = L0_buffer[3][15:0]; unaligned_valid = 1'b1; end
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// this state is only interesting if we have already done a prefetch
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2'b11: begin
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unaligned_rdata_o[31:16] = L0_buffer[0][15:0];
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unaligned_rdata[31:16] = L0_buffer[0][15:0];
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if (is_prefetch_q) begin
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unaligned_valid_o = 1'b1;
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unaligned_valid = 1'b1;
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end else begin
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unaligned_valid_o = 1'b0;
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unaligned_valid = 1'b0;
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end
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end
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endcase // addr_o
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@ -351,18 +354,18 @@ module riscv_prefetch_L0_buffer
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// icache
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case(addr_o[3:2])
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2'b00: begin unaligned_rdata_o[31:16] = instr_rdata_i[1][15:0]; unaligned_valid_o = instr_rvalid_i; end
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2'b01: begin unaligned_rdata_o[31:16] = instr_rdata_i[2][15:0]; unaligned_valid_o = instr_rvalid_i; end
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2'b10: begin unaligned_rdata_o[31:16] = instr_rdata_i[3][15:0]; unaligned_valid_o = instr_rvalid_i; end
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2'b00: begin unaligned_rdata[31:16] = instr_rdata_i[1][15:0]; unaligned_valid = instr_rvalid_i; end
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2'b01: begin unaligned_rdata[31:16] = instr_rdata_i[2][15:0]; unaligned_valid = instr_rvalid_i; end
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2'b10: begin unaligned_rdata[31:16] = instr_rdata_i[3][15:0]; unaligned_valid = instr_rvalid_i; end
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2'b11:
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begin
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unaligned_rdata_o[31:16] = instr_rdata_i[0][15:0];
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unaligned_rdata[31:16] = instr_rdata_i[0][15:0];
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if (is_prefetch_q)
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unaligned_valid_o = instr_rvalid_i;
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unaligned_valid = instr_rvalid_i;
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else
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unaligned_valid_o = 1'b0;
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unaligned_valid = 1'b0;
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end
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endcase // pointer_cs
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end
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@ -394,4 +397,11 @@ module riscv_prefetch_L0_buffer
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end
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end
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//////////////////////////////////////////////////////////////////////////////
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// instruction aligner (if unaligned)
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//////////////////////////////////////////////////////////////////////////////
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assign rdata_o = unaligned_i ? unaligned_rdata : rdata;
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assign valid_o = unaligned_i ? unaligned_valid : valid;
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endmodule // prefetch_L0_buffer
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@ -198,6 +198,7 @@ module riscv_prefetch_buffer
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input logic clk,
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input logic rst_n,
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input logic unaligned_i,
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input logic req_i,
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input logic branch_i,
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input logic ready_i,
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@ -207,9 +208,6 @@ module riscv_prefetch_buffer
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output logic [31:0] rdata_o,
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output logic [31:0] addr_o,
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output logic unaligned_valid_o,
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output logic [31:0] unaligned_rdata_o,
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// goes to instruction memory / instruction cache
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output logic instr_req_o,
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output logic [31:0] instr_addr_o,
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@ -232,6 +230,9 @@ module riscv_prefetch_buffer
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logic fifo_rdata_valid;
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logic fifo_rdata_ready;
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logic [31:0] rdata, unaligned_rdata;
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logic valid, unaligned_valid;
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//////////////////////////////////////////////////////////////////////////////
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// prefetch buffer status
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//////////////////////////////////////////////////////////////////////////////
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@ -266,15 +267,22 @@ module riscv_prefetch_buffer
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.in_rdata_ready_o ( fifo_rdata_ready ),
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.in_rdata_i ( instr_rdata_i ),
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.out_valid_o ( valid_o ),
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.out_valid_o ( valid ),
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.out_ready_i ( ready_i ),
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.out_rdata_o ( rdata_o ),
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.out_rdata_o ( rdata ),
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.out_addr_o ( addr_o ),
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.out_unaligned_valid_o ( unaligned_valid_o ),
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.out_unaligned_rdata_o ( unaligned_rdata_o )
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.out_unaligned_valid_o ( unaligned_valid ),
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.out_unaligned_rdata_o ( unaligned_rdata )
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);
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//////////////////////////////////////////////////////////////////////////////
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// instruction aligner (if unaligned)
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//////////////////////////////////////////////////////////////////////////////
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assign rdata_o = unaligned_i ? unaligned_rdata : rdata;
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assign valid_o = unaligned_i ? unaligned_valid : valid;
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//////////////////////////////////////////////////////////////////////////////
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// instruction fetch FSM
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