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[dv] Increase iterations and instructions in riscv_rf_intg_test

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This enables more scenarios begin stimulated per regression run around
RF ECC errors.
This commit is contained in:
Greg Chadwick 2024-07-15 21:14:43 +01:00 • committed by Greg Chadwick
parent 6ac0ddc46e
commit 96a1c02ba0
1 changed files with 7 additions and 1 deletions
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8
dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
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@ -683,8 +683,14 @@
- test: riscv_rf_intg_test
description: >
Randomly corrupt the register file read port once in the middle of program execution
iterations: 15
iterations: 100
gen_test: riscv_rand_instr_test
gen_opts: >
+instr_cnt=10000
+num_of_sub_program=5
+gen_all_csrs_by_default=1
+add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL,0x7c0,0x7c1
+no_csr_instr=0
rtl_test: core_ibex_rf_intg_test
rtl_params:
SecureIbex: 1