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Fix typo in signal declaration in timer.sv

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Rupert Swarbrick 2020-03-02 10:32:59 +00:00 • committed by Rupert Swarbrick
parent 5aa1585f63
commit 96f95df23d
1 changed files with 1 additions and 1 deletions
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shared/rtl/timer.sv
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@ -39,7 +39,7 @@ module timer #(
logic timer_we;
logic mtime_we, mtimeh_we;
logic mtimecmp_we, mtimcmph_we;
logic mtimecmp_we, mtimecmph_we;
logic [DataWidth-1:0] mtime_wdata, mtimeh_wdata;
logic [DataWidth-1:0] mtimecmp_wdata, mtimecmph_wdata;
logic [TW-1:0] mtime_q, mtime_d, mtime_inc;