Fix typo in last commit

This commit is contained in:
Andreas Traber 2015-10-16 14:34:33 +02:00
parent 7936609c2a
commit 97a3ded4e3

View file

@ -469,6 +469,6 @@ module riscv_load_store_unit
// there should be no rvalid when we are in IDLE
assert property (
@(posedge clk) (CS == IDLE)) |-> (data_rvalid_i == 1'b0) );
@(posedge clk) (CS == IDLE) |-> (data_rvalid_i == 1'b0) );
endmodule