[doc] Update coverage plan to point crosses/cp's

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>

doc/03_reference/coverage_plan.rst

@@ -127,6 +127,7 @@ Ibex hazards all occur in the interaction between the ID and EX stage.
     Handled with data forwarding and no stall.
 
 * RAW Load/Store bytes - Load with bytes overlapping a store immediately before it.
+  Covered by ``cp_mem_raw_hz``
 
 State Specific Behaviour
 """"""""""""""""""""""""
@@ -157,6 +158,7 @@ Some instructions will behave differently depending upon the state of the proces
     * ``tdata3``
 
 * Loads/stores with ``mstatus.mprv`` set and unset.
+  Covered by ````mprv_effect_cross``
 * EBreak behaviour in U/M mode with different ``dcsr.ebreakm`` / ``dcsr.ebreaku`` settings.
   Covered by ``priv_mode_instr_cross``
 
@@ -216,18 +218,19 @@ Furthermore they can all occur together and must be appropriately prioritised (c
   * Instruction matching trigger point causes exception
 
 * Ibex operating in debug mode.
-* Debug and Interrupt whilst sleeping with WFI
+* ``irq_wfi_cross``, ``debug_wfi_cross`` - Debug and Interrupt whilst sleeping with WFI
 
   * Cover with global interrupts enabled and disabled
   * Cover with specific interrupt enabled and disabled (Should exit sleep when
     interrupt is enabled but global interrupts set to disabled, should continue
     sleeping when both are disabled).
+    Continuing to sleep in the case explained above is covered by ``cp_irq_continue_sleep``
 
 * Debug and interrupt occurring whilst entering WFI
 
   * Covering period between WFI entering ID/EX stage and going into sleep
 
-* Double fault
+* ``cp_double_fault`` - Double fault
 
 PMP
 ^^^
@@ -279,13 +282,13 @@ Basic read/write functionality must be tested on all implemented CSRs.
   * Write to read only CSR.
     Covered by ensuring ``cp_csr_write`` is seen for read-only CSRs
 
-* Write illegal/unsupported value to WARL field.
+* ``cp_warl_check_CSRNAME`` - Write illegal/unsupported value to WARL field for CSR named ``CSRNAME``.
 * ``csr_read_only_priv_cross``, ``csr_write_priv_cross``, ``csr_read_only_debug_cross``, ``csr_write_debug_cross`` - Crosses of reads and writes to CSRs from different privilege levels/debug mode.
 
   * Access to CSR disallowed due to privilege levels/debug mode
     Covered by ensuring within the crosses
 
-* Read and write from/to an unimplemented CSR
+* ``cp_ignored_csrs_ro``, ``cp_ignored_csrs_w`` - Read and write from/to an unimplemented CSR
 
 CSRs addresses do not need to be crossed with the variety of CSR instructions as these all use the same basic read & write interface into ``ibex_cs_registers``.
 Coverage of the above points will be sampled at the ``ibex_cs_registers`` interface (as opposed to sampling CSR instructions).
@@ -295,7 +298,7 @@ Miscellaneous
 Various points of interest do not fit into the categories above.
 
 * ``instr_unstalled`` - Instruction unstalled - Cover the cycle an instruction is unstalled having just been stalled.
-* Enabling/Disabling ICache.
+* ``cp_icache_enable`` - Enabling/Disabling ICache.
 
 Cross Coverage
 --------------
@@ -326,7 +329,7 @@ There must be a documented reason a particular bin is added to the illegal or ig
   * RAW hazard between load/store requires no cross coverage as it's only seen for load and store instructions so the single coverpoint suffices.
 
 * ``debug_instruction_cross`` - Instruction Categories x Debug Mode
-* Instruction Categories x Controller state transitions of interest
+* ``controller_instr_cross`` - Instruction Categories x Controller state transitions of interest
 * ``interrupt_taken_instr_cross``, ``debug_entry_if_instr_cross``, ``pipe_flush_instr_cross`` - Interrupt taken/Debug mode entry/Pipe flush x instruction unstalled x instruction category
 
   * Three separate cross coverage groups: one for interrupt, debug and pipe flush.