[fpga] Add power analysis scripts to FPGA example

This commit adds power analysis scripts to the Arty A7
example design. They can be used by setting the newly
added `FPGAPowerAnalysis` parameter to 1.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>

examples/fpga/artya7/README.md

@@ -73,6 +73,17 @@ Please see [CoreMark README](https://github.com/lowRISC/ibex/blob/master/example
 fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1 --SRAMInitFile=examples/sw/benchmarks/coremark/coremark.vmem
 ```
 
+#### Power Analysis Using Vivado
+
+Setting `FPGAPowerAnalysis` parameter to 1 allows user to run a power analysis using Vivado.
+It uses a post-implementation functional simulation on Vivado to log switching activity.
+This switching activity is then used to generate a detailed power report.
+In order to use it with CoreMark run the command below
+
+```
+fusesoc --cores-root=. run --target=synth --setup --build lowrisc:ibex:top_artya7 --part xc7a100tcsg324-1 --SRAMInitFile=examples/sw/benchmarks/coremark/coremark.vmem --FPGAPowerAnalysis=1
+```
+
 ## Program
 
 After the board is connected to the computer it can be programmed with:

examples/fpga/artya7/top_artya7.core

@@ -18,6 +18,11 @@ filesets:
       - data/pins_artya7.xdc
     file_type: xdc
 
+  files_tcl:
+    files:
+      - util/vivado_setup_hooks.tcl : { file_type: tclSource }
+      - util/vivado_hook_write_bitstream_pre.tcl : { file_type: user, copyto: vivado_hook_write_bitstream_pre.tcl }
+
 parameters:
   # XXX: This parameter needs to be absolute, or relative to the *.runs/synth_1
   # directory. It's best to pass it as absolute path when invoking fusesoc, e.g.
@@ -36,6 +41,11 @@ parameters:
     datatype: str
     paramtype: vlogdefine
     description: Primitives implementation to use, e.g. "prim_pkg::ImplGeneric".
+ 
+  FPGAPowerAnalysis:
+    datatype: int
+    paramtype: vlogparam
+    description: Enables custom power analysis scripts for Vivado.
 
 targets:
   synth:
@@ -43,10 +53,12 @@ targets:
     filesets:
       - files_rtl_artya7
       - files_constraints
+      - files_tcl
     toplevel: top_artya7
     parameters:
       - SRAMInitFile
       - PRIM_DEFAULT_IMPL=prim_pkg::ImplXilinx
+      - FPGAPowerAnalysis
     tools:
       vivado:
         part: "xc7a100tcsg324-1"  # Default to Arty A7-100

examples/fpga/artya7/util/vivado_hook_write_bitstream_pre.tcl

@@ -0,0 +1,24 @@
+open_project ../../lowrisc_ibex_top_artya7_0.1.xpr
+set saif_name "detailed_power.saif"
+
+open_run impl_1
+
+# Runs a post implementation functional simulation with the memory initialized with SRAMInitFile.
+# Feeds clock (100mhz) and reset switch and records switching activity for 3ms.
+set_property top top_artya7 [current_fileset sim_1]
+launch_simulation -mode post-implementation -type functional
+open_saif "$saif_name"
+log_saif [get_objects -r *]
+add_force {/top_artya7/IO_CLK} -radix bin {1 0ns} {0 5ns} -repeat_every 10ns
+add_force {/top_artya7/IO_RST_N} -radix bin {1 0ns}
+run 3ms
+close_saif
+
+
+# Reporting power using .saif generated above
+open_run impl_1
+set_operating_conditions -process maximum
+read_saif "../../lowrisc_ibex_top_artya7_0.1.sim/sim_1/impl/func/xsim/$saif_name" 
+read_saif "../../lowrisc_ibex_top_artya7_0.1.sim/sim_1/impl/func/xsim/$saif_name"  -strip_path top_artya7 
+set_units -power uW
+report_power -name {detailed_power_report} -verbose -file post_implementation_power_result.log -hierarchical_depth 20

examples/fpga/artya7/util/vivado_setup_hooks.tcl

@@ -0,0 +1,14 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Setup hook scripts, to be called at various stages during the build process
+# See Xilinx UG 894 ("Using Tcl Scripting") for documentation.
+
+# fusesoc-generated workroot containing the Vivado project file
+set workroot [pwd]
+set vlogparam_list [get_property generic [get_filesets sources_1]]
+set FPGAPowerAnalysis [regexp {FPGAPowerAnalysis} $vlogparam_list]
+if {$FPGAPowerAnalysis == 1} {
+        set_property STEPS.WRITE_BITSTREAM.TCL.PRE "${workroot}/vivado_hook_write_bitstream_pre.tcl" [get_runs impl_1]
+}