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[DV] Update implemented CSRs (#345)

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udinator 2019-09-23 15:59:10 -07:00 • committed by GitHub
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74
dv/uvm/riscv_dv_extension/riscv_core_setting.sv
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@ -73,15 +73,67 @@ int kernel_program_instr_cnt = 400;
// Implemented previlieged CSR list
privileged_reg_t implemented_csr[$] = {
// Machine mode mode CSR
MVENDORID, // Vendor ID
MARCHID, // Architecture ID
MHARTID, // Hardware thread ID
MSTATUS, // Machine status
MISA, // ISA and extensions
MTVEC, // Machine trap-handler base address
MEPC, // Machine exception program counter
MCAUSE, // Machine trap cause
MTVAL, // Machine bad address or instruction
MIE // Machine interrupt enable
// TODO: Add performance CSRs and debug mode CSR
MVENDORID, // Vendor ID
MARCHID, // Architecture ID
MHARTID, // Hardware thread ID
MSTATUS, // Machine status
MISA, // ISA and extensions
MTVEC, // Machine trap-handler base address
MEPC, // Machine exception program counter
MCAUSE, // Machine trap cause
MTVAL, // Machine bad address or instruction
MIE, // Machine interrupt enable
MCYCLE, // Machine cycle counter (lower 32 bits)
MCYCLEH, // Machine cycle counter (upper 32 bits)
MINSTRET, // Machine instructions retired counter (lower 32 bits)
MINSTRETH, // Machine instructions retired counter (upper 32 bits)
MCOUNTINHIBIT, // Machine counter inhibit register
MHPMEVENT3, // Machine performance monitoring event selector
MHPMEVENT4, // Machine performance monitoring event selector
MHPMEVENT5, // Machine performance monitoring event selector
MHPMEVENT6, // Machine performance monitoring event selector
MHPMEVENT7, // Machine performance monitoring event selector
MHPMEVENT8, // Machine performance monitoring event selector
MHPMEVENT9, // Machine performance monitoring event selector
MHPMEVENT10, // Machine performance monitoring event selector
MHPMCOUNTER3, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER4, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER5, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER6, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER7, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER8, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER9, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER10, // Machine performance monitoring counter (lower 32 bits)
MHPMCOUNTER3H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER4H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER5H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER6H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER7H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER8H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER9H, // Machine performance monitoring counter (upper 32 bits)
MHPMCOUNTER10H, // Machine performance monitoring counter (upper 32 bits)
PMPCFG0, // PMP configuration register
PMPCFG1, // PMP configuration register
PMPCFG2, // PMP configuration register
PMPCFG3, // PMP configuration register
PMPADDR0, // PMP address register
PMPADDR1, // PMP address register
PMPADDR2, // PMP address register
PMPADDR3, // PMP address register
PMPADDR4, // PMP address register
PMPADDR5, // PMP address register
PMPADDR6, // PMP address register
PMPADDR7, // PMP address register
PMPADDR8, // PMP address register
PMPADDR9, // PMP address register
PMPADDR10, // PMP address register
PMPADDR11, // PMP address register
PMPADDR12, // PMP address register
PMPADDR13, // PMP address register
PMPADDR14, // PMP address register
PMPADDR15, // PMP address register
DCSR, // Debug control and status register
DPC, // Debug PC
DSCRATCH0, // Debug scratch register 0
DSCRATCH1 // Debug scratch register 1
};