[DV] Add test to assert interrupts during debug execution (#524)

dv/uvm/riscv_dv_extension/testlist.yaml

@@ -280,6 +280,7 @@
     +require_signature_addr=1
     +gen_debug_section=1
     +randomize_csr=1
+    +no_csr_instr=1
     +enable_dummy_csr_write=1
     +boot_mode=m
   rtl_test: core_ibex_debug_csr_test
@@ -289,6 +290,25 @@
   compare_opts:
     compare_final_value_only: 1
 
+- test: riscv_irq_in_debug_mode_test
+  description: >
+    Send interrupts while the core is executing in debug mode, should ignore everything
+  iterations: 10
+  gen_test: riscv_rand_instr_test
+  gen_opts: >
+    +require_signature_addr=1
+    +gen_debug_section=1
+    +randomize_csr=1
+    +no_csr_instr=1
+    +no_fence=1
+  rtl_test: core_ibex_debug_irq_test
+  sim_opts: >
+    +require_signature_addr=1
+    +enable_debug_seq=1
+    +enable_irq_multiple_seq=1
+  compare_opts:
+    compare_final_value_only: 1
+
 - test: riscv_single_interrupt_test
   description: >
     Random instruction test with complete interrupt handling

dv/uvm/tests/core_ibex_test_lib.sv

@@ -484,6 +484,43 @@ class core_ibex_irq_csr_test extends core_ibex_directed_test;
 
 endclass
 
+// Debug mode IRQ test
+class core_ibex_debug_irq_test extends core_ibex_directed_test;
+
+  `uvm_component_utils(core_ibex_debug_irq_test)
+  `uvm_component_new
+
+  virtual task check_stimulus();
+    bit detected_irq = 1'b0;
+    forever begin
+      // Drive core into debug mode
+      vseq.start_debug_single_seq();
+      check_next_core_status(IN_DEBUG_MODE, "Core did not enter debug mode properly", 1000);
+      check_priv_mode(PRIV_LVL_M);
+      wait_for_csr_write(CSR_DCSR, 500);
+      check_dcsr_prv(operating_mode);
+      check_dcsr_cause(DBG_CAUSE_HALTREQ);
+      clk_vif.wait_clks($urandom_range(50, 100));
+      // Raise interrupts while the core is in debug mode
+      vseq.start_irq_raise_seq();
+      fork
+        begin : wait_irq
+          wait_for_core_status(HANDLING_IRQ);
+          `uvm_fatal(`gfn, "Core is handling interrupt detected in debug mode")
+        end
+        begin
+          clk_vif.wait_clks(500);
+          disable wait_irq;
+        end
+      join
+      vseq.start_irq_drop_seq();
+      wait_ret("dret", 5000);
+      clk_vif.wait_clks($urandom_range(250, 500));
+    end
+  endtask
+
+endclass
+
 // Debug WFI test class
 class core_ibex_debug_wfi_test extends core_ibex_directed_test;