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Fix RegFile parameter overriding in ArtyA7 example

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Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
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Pirmin Vogel 2020-08-21 14:49:12 +02:00 • committed by Rupert Swarbrick
parent 62109d4044
commit 9eebf52590
1 changed files with 1 additions and 1 deletions
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examples/fpga/artya7/rtl/top_artya7.sv
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@ -43,7 +43,7 @@ module top_artya7 (
ibex_core #(
.RegFile(RegFileFPGA),
.RegFile(ibex_pkg::RegFileFPGA),
.DmHaltAddr(32'h00000000),
.DmExceptionAddr(32'h00000000)
) u_core (