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https://github.com/lowRISC/ibex.git
synced 2025-04-22 12:57:13 -04:00
Fix control for interrupts, debug request and multicycle instr
This commit makes sure that interrupts and debug requests do not interrupt currently running multicycle instructions. Priority is given 1) to the currently running instruction, possible exceptions caused by this instruction, 2) debug requests, 3) interrupt requests. Previously, currently running instructions were aborted upon incoming debug and interrupt requests, which could corrupt the processor state and lead to exceptions being ignored. This commit resolves #108 and #121.
This commit is contained in:
Pirmin Vogel
parent
fd6426f52c
commit
9ef3c13f87
2 changed files with 56 additions and 49 deletions
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@ -53,7 +53,7 @@ module ibex_controller (
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// to IF-ID pipeline stage
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output logic instr_valid_clear_o, // kill instr in IF-ID reg
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output logic id_ready_o, // ID stage is ready for new instr
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output logic halt_if_o, // request halt of IF stage
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output logic halt_if_o, // IF stage must not forward new instr
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// to prefetcher
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output logic instr_req_o, // start fetching instructions
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@ -126,13 +126,14 @@ module ibex_controller (
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ctrl_fsm_e ctrl_fsm_cs, ctrl_fsm_ns;
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logic irq_enable_int;
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logic debug_mode_q, debug_mode_n;
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logic load_err_q, load_err_n;
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logic store_err_q, store_err_n;
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logic stall;
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logic halt_id;
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logic irq;
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logic special_req;
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`ifndef SYNTHESIS
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// synopsys translate_off
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@ -148,6 +149,12 @@ module ibex_controller (
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// synopsys translate_on
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`endif
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assign irq = irq_req_ctrl_i & m_IE_i;
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assign exc_kill_o = 1'b0;
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// special requests: special instructions, exceptions, pipeline flushes...
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assign special_req = mret_insn_i | dret_insn_i | ecall_insn_i | ebrk_insn_i | wfi_insn_i |
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illegal_insn_i | store_err_i | load_err_i | csr_status_i;
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/////////////////////
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// Core controller //
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@ -158,7 +165,6 @@ module ibex_controller (
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instr_req_o = 1'b1;
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exc_ack_o = 1'b0;
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exc_kill_o = 1'b0;
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csr_save_if_o = 1'b0;
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csr_save_id_o = 1'b0;
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@ -183,7 +189,6 @@ module ibex_controller (
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halt_id = 1'b0;
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irq_ack_o = 1'b0;
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irq_id_o = irq_id_ctrl_i;
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irq_enable_int = m_IE_i;
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debug_csr_save_o = 1'b0;
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debug_cause_o = DBG_CAUSE_EBREAK;
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@ -247,7 +252,7 @@ module ibex_controller (
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end
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// handle interrupts
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if (irq_req_ctrl_i && irq_enable_int) begin
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if (irq) begin
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// This assumes that the pipeline is always flushed before
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// going to sleep.
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ctrl_fsm_ns = IRQ_TAKEN;
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@ -264,60 +269,57 @@ module ibex_controller (
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end
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DECODE: begin
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is_decoding_o = 1'b0;
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// normal operating mode of the ID stage, in case of debug and interrupt requests,
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// priorities are as follows (lower number == higher priority)
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// 1. currently running (multicycle) instructions and exceptions caused by these
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// 2. debug requests
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// 3. interrupt requests
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/*
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* TODO: What should happen on
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* instr_valid_i && (instr_multicycle_i || branch_in_id_i)?
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* Let the instruction finish executing before serving debug or
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* interrupt requests?
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*/
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if (instr_valid_i) begin
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// analyze current instruction in ID stage
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is_decoding_o = 1'b1;
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unique case (1'b1)
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debug_req_i && !debug_mode_q: begin
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// Enter debug mode from external request
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ctrl_fsm_ns = DBG_TAKEN_ID;
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halt_if_o = 1'b1;
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halt_id = 1'b1;
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end
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// set PC in IF stage to branch or jump target
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if (branch_set_i || jump_set_i) begin
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pc_mux_o = PC_JUMP;
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pc_set_o = 1'b1;
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irq_req_ctrl_i && irq_enable_int && !debug_req_i && !debug_mode_q: begin
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// Serve an interrupt (not in debug mode)
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ctrl_fsm_ns = IRQ_TAKEN;
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perf_tbranch_o = branch_set_i;
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perf_jump_o = jump_set_i;
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// get ready for special instructions, exceptions, pipeline flushes
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end else if (special_req) begin
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ctrl_fsm_ns = FLUSH;
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halt_if_o = 1'b1;
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halt_id = 1'b1;
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load_err_n = load_err_i;
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store_err_n = store_err_i;
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end
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default: begin
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exc_kill_o = irq_req_ctrl_i & ~instr_multicycle_i & ~branch_in_id_i;
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if (instr_valid_i) begin
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// analyze the current instruction in the ID stage
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is_decoding_o = 1'b1;
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if (branch_set_i || jump_set_i) begin
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pc_mux_o = PC_JUMP;
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pc_set_o = 1'b1;
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perf_tbranch_o = branch_set_i;
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perf_jump_o = jump_set_i;
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end else if (mret_insn_i || dret_insn_i || ecall_insn_i || wfi_insn_i ||
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ebrk_insn_i || illegal_insn_i || csr_status_i ||
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store_err_i || load_err_i) begin
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ctrl_fsm_ns = FLUSH;
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halt_if_o = 1'b1;
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halt_id = 1'b1;
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load_err_n = load_err_i;
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store_err_n = store_err_i;
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end
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end
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// stall IF stage to not starve debug and interrupt requests, these just
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// need to wait until after the current (multicycle) instruction
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if ((debug_req_i || irq) && stall && !debug_mode_q) begin
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halt_if_o = 1'b1;
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end
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endcase
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end
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if (debug_req_i && !stall && !special_req && !debug_mode_q) begin
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// enter debug mode
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ctrl_fsm_ns = DBG_TAKEN_ID;
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halt_if_o = 1'b1;
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halt_id = 1'b1;
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end else if (irq && !stall && !special_req && !debug_mode_q) begin
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// handle interrupt (not in debug mode)
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ctrl_fsm_ns = IRQ_TAKEN;
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halt_if_o = 1'b1;
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halt_id = 1'b1;
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end
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// Single stepping
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// prevent any more instructions from executing
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if (debug_single_step_i && !debug_mode_q) begin
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halt_if_o = 1'b1;
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halt_if_o = 1'b1;
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ctrl_fsm_ns = DBG_TAKEN_IF;
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end
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end
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@ -520,13 +522,17 @@ module ibex_controller (
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// Stall control //
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///////////////////
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// current instr needs at least one more cycle to finsih after the current cycle
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// if low, current instr finsihes in current cycle
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assign stall = stall_lsu_i | stall_multdiv_i | stall_jump_i | stall_branch_i;
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// deassert write enable when the core is not decoding instructions, i.e., current instruction
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// in ID stage done, but waiting for next instruction from IF stage, or in case of illegal
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// instruction
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assign deassert_we_o = ~is_decoding_o | illegal_insn_i;
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// signal to IF stage that ID stage is ready for next instruction
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assign id_ready_o = ~stall_lsu_i & ~stall_multdiv_i & ~stall_jump_i & ~stall_branch_i;
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assign id_ready_o = ~stall;
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// kill instruction in IF-ID reg for instructions that are done
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assign instr_valid_clear_o = id_ready_o | halt_id;
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@ -636,6 +636,7 @@ module ibex_id_stage #(
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WAIT_MULTICYCLE: begin
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if ((data_req_dec & lsu_valid_i) | (~data_req_dec & ex_valid_i)) begin
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id_wb_fsm_ns = IDLE;
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instr_multicycle = 1'b1;
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instr_multicycle_done_n = 1'b1;
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end else begin
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regfile_we = 1'b0;
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