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Add register for last branch PC

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Needed in the debug unit, could be reused for precise exceptions.
This commit is contained in:
Sven Stucki 2015-10-27 17:50:44 +01:00
parent 05b44f97c0
commit 9efbaeba63
3 changed files with 28 additions and 7 deletions
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12
debug_unit.sv
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@ -5,6 +5,7 @@
// //
// Additional contributions by: //
// Andreas Traber - atraber@student.ethz.ch //
// Sven Stucki - svstucki@student.ethz.ch //
// //
// //
// Create Date: 11/07/2014 //
@ -60,6 +61,7 @@ module riscv_debug_unit
// Signals for PPC & NPC register
input logic [31:0] curr_pc_if_i,
input logic [31:0] curr_pc_id_i,
input logic [31:0] branch_pc_i,
output logic [31:0] npc_o,
output logic set_npc_o
@ -78,10 +80,10 @@ module riscv_debug_unit
always_comb
begin
BP_State_SN = BP_State_SP;
stall_core_o = 1'b0;
dbginf_bp_o = 1'b0;
flush_pipe_o = 1'b0;
BP_State_SN = BP_State_SP;
stall_core_o = 1'b0;
dbginf_bp_o = 1'b0;
flush_pipe_o = 1'b0;
case (BP_State_SP)
Idle:
@ -149,7 +151,7 @@ module riscv_debug_unit
// address decoding, first stage: evaluate higher 5 Bits to detect if debug regs are accessed
if(dbginf_addr_i[15:11] == 5'b00110) begin
// second stage: evaluate Bits 10:0 to detect which part of debug registers is accessed
casex(dbginf_addr_i[10:0])
case (dbginf_addr_i[10:0])
11'd0: begin // NPC
set_npc_o = dbginf_we_i;

16
id_stage.sv
View file

@ -80,7 +80,9 @@ module riscv_id_stage
input logic ex_valid_i, // EX stage is done
input logic wb_valid_i, // WB stage is done
// To the Pipeline ID/EX
// Pipeline ID/EX
output logic [31:0] branch_pc_ex_o,
output logic [31:0] alu_operand_a_ex_o,
output logic [31:0] alu_operand_b_ex_o,
output logic [31:0] alu_operand_c_ex_o,
@ -817,6 +819,18 @@ module riscv_id_stage
// |___|____/ |_____/_/\_\ |_| |___|_| |_____|_____|___|_| \_|_____| //
// //
/////////////////////////////////////////////////////////////////////////////////
always_ff @(posedge clk, negedge rst_n)
begin
if (rst_n == 1'b0)
begin
branch_pc_ex_o <= '0;
end
else begin
if (jump_in_id_o == `BRANCH_COND && id_valid_o)
branch_pc_ex_o <= current_pc_id_i;
end
end
always_ff @(posedge clk, negedge rst_n)
begin : ID_EX_PIPE_REGISTERS
if (rst_n == 1'b0)

7
riscv_core.sv
View file

@ -113,6 +113,8 @@ module riscv_core
logic if_busy;
logic [31:0] branch_pc_ex; // PC of last executed branch
// ALU Control
logic [`ALU_OP_WIDTH-1:0] alu_operator_ex;
logic [31:0] alu_operand_a_ex;
@ -346,6 +348,7 @@ module riscv_core
.wb_valid_i ( wb_valid ),
// From the Pipeline ID/EX
.branch_pc_ex_o ( branch_pc_ex ),
.alu_operand_a_ex_o ( alu_operand_a_ex ),
.alu_operand_b_ex_o ( alu_operand_b_ex ),
.alu_operand_c_ex_o ( alu_operand_c_ex ),
@ -626,13 +629,14 @@ module riscv_core
// To/From Core
.dbg_st_en_o ( dbg_st_en ),
.dbg_dsr_o ( dbg_dsr ),
.stall_core_o ( dbg_stall ),
.flush_pipe_o ( dbg_flush_pipe ),
.trap_i ( dbg_trap ),
// register file access
.regfile_mux_o ( dbg_reg_mux ),
.sp_mux_o ( dbg_sp_mux ),
.regfile_mux_o ( dbg_reg_mux ),
.regfile_we_o ( dbg_reg_we ),
.regfile_addr_o ( dbg_reg_addr ),
.regfile_wdata_o ( dbg_reg_wdata ),
@ -641,6 +645,7 @@ module riscv_core
// signals for PPC and NPC
.curr_pc_if_i ( current_pc_if ), // from IF stage
.curr_pc_id_i ( current_pc_id ), // from IF stage
.branch_pc_i ( branch_pc_ex ), // PC of last executed branch (in EX stage)
.npc_o ( dbg_npc ), // PC from debug unit
.set_npc_o ( dbg_set_npc ) // set PC to new value
);