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https://github.com/lowRISC/ibex.git
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[style] Indent module header with two spaces
Both the parameter and the port list in a module header should be indented with two spaces, according to our style guide.
This commit is contained in:
Philipp Wagner
Philipp Wagner
parent
87bcd13a12
commit
a25790abf9
23 changed files with 1116 additions and 1116 deletions
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@ -9,27 +9,27 @@
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module ibex_alu #(
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parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone
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) (
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input ibex_pkg::alu_op_e operator_i,
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input logic [31:0] operand_a_i,
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input logic [31:0] operand_b_i,
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input ibex_pkg::alu_op_e operator_i,
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input logic [31:0] operand_a_i,
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input logic [31:0] operand_b_i,
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input logic instr_first_cycle_i,
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input logic instr_first_cycle_i,
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input logic [32:0] multdiv_operand_a_i,
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input logic [32:0] multdiv_operand_b_i,
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input logic [32:0] multdiv_operand_a_i,
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input logic [32:0] multdiv_operand_b_i,
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input logic multdiv_sel_i,
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input logic multdiv_sel_i,
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input logic [31:0] imd_val_q_i[2],
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output logic [31:0] imd_val_d_o[2],
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output logic [1:0] imd_val_we_o,
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input logic [31:0] imd_val_q_i[2],
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output logic [31:0] imd_val_d_o[2],
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output logic [1:0] imd_val_we_o,
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output logic [31:0] adder_result_o,
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output logic [33:0] adder_result_ext_o,
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output logic [31:0] adder_result_o,
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output logic [33:0] adder_result_ext_o,
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output logic [31:0] result_o,
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output logic comparison_result_o,
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output logic is_equal_result_o
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output logic [31:0] result_o,
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output logic comparison_result_o,
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output logic is_equal_result_o
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);
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import ibex_pkg::*;
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@ -14,13 +14,13 @@
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`include "prim_assert.sv"
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module ibex_compressed_decoder (
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input logic clk_i,
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input logic rst_ni,
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input logic valid_i,
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input logic [31:0] instr_i,
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output logic [31:0] instr_o,
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output logic is_compressed_o,
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output logic illegal_instr_o
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input logic clk_i,
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input logic rst_ni,
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input logic valid_i,
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input logic [31:0] instr_i,
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output logic [31:0] instr_o,
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output logic is_compressed_o,
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output logic illegal_instr_o
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);
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import ibex_pkg::*;
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@ -11,103 +11,103 @@
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`include "dv_fcov_macros.svh"
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module ibex_controller #(
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parameter bit WritebackStage = 0,
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parameter bit BranchPredictor = 0
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parameter bit WritebackStage = 0,
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parameter bit BranchPredictor = 0
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) (
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input logic clk_i,
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input logic rst_ni,
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input logic clk_i,
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input logic rst_ni,
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output logic ctrl_busy_o, // core is busy processing instrs
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output logic ctrl_busy_o, // core is busy processing instrs
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// decoder related signals
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input logic illegal_insn_i, // decoder has an invalid instr
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input logic ecall_insn_i, // decoder has ECALL instr
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input logic mret_insn_i, // decoder has MRET instr
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input logic dret_insn_i, // decoder has DRET instr
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input logic wfi_insn_i, // decoder has WFI instr
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input logic ebrk_insn_i, // decoder has EBREAK instr
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input logic csr_pipe_flush_i, // do CSR-related pipeline flush
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// decoder related signals
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input logic illegal_insn_i, // decoder has an invalid instr
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input logic ecall_insn_i, // decoder has ECALL instr
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input logic mret_insn_i, // decoder has MRET instr
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input logic dret_insn_i, // decoder has DRET instr
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input logic wfi_insn_i, // decoder has WFI instr
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input logic ebrk_insn_i, // decoder has EBREAK instr
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input logic csr_pipe_flush_i, // do CSR-related pipeline flush
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// instr from IF-ID pipeline stage
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input logic instr_valid_i, // instr is valid
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input logic [31:0] instr_i, // uncompressed instr data for mtval
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input logic [15:0] instr_compressed_i, // instr compressed data for mtval
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input logic instr_is_compressed_i, // instr is compressed
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input logic instr_bp_taken_i, // instr was predicted taken branch
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input logic instr_fetch_err_i, // instr has error
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input logic instr_fetch_err_plus2_i, // instr error is x32
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input logic [31:0] pc_id_i, // instr address
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// instr from IF-ID pipeline stage
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input logic instr_valid_i, // instr is valid
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input logic [31:0] instr_i, // uncompressed instr data for mtval
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input logic [15:0] instr_compressed_i, // instr compressed data for mtval
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input logic instr_is_compressed_i, // instr is compressed
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input logic instr_bp_taken_i, // instr was predicted taken branch
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input logic instr_fetch_err_i, // instr has error
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input logic instr_fetch_err_plus2_i, // instr error is x32
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input logic [31:0] pc_id_i, // instr address
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// to IF-ID pipeline stage
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output logic instr_valid_clear_o, // kill instr in IF-ID reg
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output logic id_in_ready_o, // ID stage is ready for new instr
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output logic controller_run_o, // Controller is in standard instruction
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// run mode
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// to IF-ID pipeline stage
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output logic instr_valid_clear_o, // kill instr in IF-ID reg
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output logic id_in_ready_o, // ID stage is ready for new instr
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output logic controller_run_o, // Controller is in standard instruction
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// run mode
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// to prefetcher
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output logic instr_req_o, // start fetching instructions
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output logic pc_set_o, // jump to address set by pc_mux
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output logic pc_set_spec_o, // speculative branch
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output ibex_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector
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// (boot, normal, exception...)
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output logic nt_branch_mispredict_o, // Not-taken branch in ID/EX was
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// mispredicted (predicted taken)
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output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC
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output ibex_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs
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// to prefetcher
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output logic instr_req_o, // start fetching instructions
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output logic pc_set_o, // jump to address set by pc_mux
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output logic pc_set_spec_o, // speculative branch
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output ibex_pkg::pc_sel_e pc_mux_o, // IF stage fetch address selector
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// (boot, normal, exception...)
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output logic nt_branch_mispredict_o, // Not-taken branch in ID/EX was
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// mispredicted (predicted taken)
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output ibex_pkg::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC
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output ibex_pkg::exc_cause_e exc_cause_o, // for IF stage, CSRs
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// LSU
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input logic [31:0] lsu_addr_last_i, // for mtval
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input logic load_err_i,
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input logic store_err_i,
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output logic wb_exception_o, // Instruction in WB taking an exception
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// LSU
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input logic [31:0] lsu_addr_last_i, // for mtval
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input logic load_err_i,
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input logic store_err_i,
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output logic wb_exception_o, // Instruction in WB taking an exception
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// jump/branch signals
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input logic branch_set_i, // branch set signal (branch definitely
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// taken)
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input logic branch_set_spec_i, // speculative branch signal (branch
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// may be taken)
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input logic branch_not_set_i, // branch is definitely not taken
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input logic jump_set_i, // jump taken set signal
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// jump/branch signals
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input logic branch_set_i, // branch set signal (branch definitely
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// taken)
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input logic branch_set_spec_i, // speculative branch signal (branch
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// may be taken)
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input logic branch_not_set_i, // branch is definitely not taken
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input logic jump_set_i, // jump taken set signal
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// interrupt signals
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input logic csr_mstatus_mie_i, // M-mode interrupt enable bit
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input logic irq_pending_i, // interrupt request pending
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input ibex_pkg::irqs_t irqs_i, // interrupt requests qualified with
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// mie CSR
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input logic irq_nm_i, // non-maskeable interrupt
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output logic nmi_mode_o, // core executing NMI handler
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// interrupt signals
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input logic csr_mstatus_mie_i, // M-mode interrupt enable bit
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input logic irq_pending_i, // interrupt request pending
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input ibex_pkg::irqs_t irqs_i, // interrupt requests qualified with
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// mie CSR
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input logic irq_nm_i, // non-maskeable interrupt
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output logic nmi_mode_o, // core executing NMI handler
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// debug signals
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input logic debug_req_i,
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output ibex_pkg::dbg_cause_e debug_cause_o,
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output logic debug_csr_save_o,
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output logic debug_mode_o,
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input logic debug_single_step_i,
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input logic debug_ebreakm_i,
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input logic debug_ebreaku_i,
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input logic trigger_match_i,
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// debug signals
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input logic debug_req_i,
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output ibex_pkg::dbg_cause_e debug_cause_o,
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output logic debug_csr_save_o,
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output logic debug_mode_o,
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input logic debug_single_step_i,
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input logic debug_ebreakm_i,
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input logic debug_ebreaku_i,
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input logic trigger_match_i,
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output logic csr_save_if_o,
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output logic csr_save_id_o,
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output logic csr_save_wb_o,
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output logic csr_restore_mret_id_o,
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output logic csr_restore_dret_id_o,
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output logic csr_save_cause_o,
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output logic [31:0] csr_mtval_o,
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input ibex_pkg::priv_lvl_e priv_mode_i,
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input logic csr_mstatus_tw_i,
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output logic csr_save_if_o,
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output logic csr_save_id_o,
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output logic csr_save_wb_o,
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output logic csr_restore_mret_id_o,
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output logic csr_restore_dret_id_o,
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output logic csr_save_cause_o,
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output logic [31:0] csr_mtval_o,
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input ibex_pkg::priv_lvl_e priv_mode_i,
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input logic csr_mstatus_tw_i,
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// stall & flush signals
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input logic stall_id_i,
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input logic stall_wb_i,
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output logic flush_id_o,
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input logic ready_wb_i,
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// stall & flush signals
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input logic stall_id_i,
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input logic stall_wb_i,
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output logic flush_id_o,
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input logic ready_wb_i,
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// performance monitors
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output logic perf_jump_o, // we are executing a jump
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// instruction (j, jr, jal, jalr)
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output logic perf_tbranch_o // we are executing a taken branch
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// instruction
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// performance monitors
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output logic perf_jump_o, // we are executing a jump
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// instruction (j, jr, jal, jalr)
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output logic perf_tbranch_o // we are executing a taken branch
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// instruction
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);
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import ibex_pkg::*;
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220
rtl/ibex_core.sv
220
rtl/ibex_core.sv
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@ -13,128 +13,128 @@
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* Top level module of the ibex RISC-V core
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*/
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module ibex_core import ibex_pkg::*; #(
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parameter bit PMPEnable = 1'b0,
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parameter int unsigned PMPGranularity = 0,
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parameter int unsigned PMPNumRegions = 4,
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parameter int unsigned MHPMCounterNum = 0,
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parameter int unsigned MHPMCounterWidth = 40,
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parameter bit RV32E = 1'b0,
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parameter rv32m_e RV32M = RV32MFast,
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parameter rv32b_e RV32B = RV32BNone,
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parameter bit BranchTargetALU = 1'b0,
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parameter bit WritebackStage = 1'b0,
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parameter bit ICache = 1'b0,
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parameter bit ICacheECC = 1'b0,
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parameter int unsigned BusSizeECC = BUS_SIZE,
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parameter int unsigned TagSizeECC = IC_TAG_SIZE,
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parameter int unsigned LineSizeECC = IC_LINE_SIZE,
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parameter bit BranchPredictor = 1'b0,
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parameter bit DbgTriggerEn = 1'b0,
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parameter int unsigned DbgHwBreakNum = 1,
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parameter bit ResetAll = 1'b0,
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parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
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parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
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parameter bit SecureIbex = 1'b0,
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parameter bit DummyInstructions = 1'b0,
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parameter bit RegFileECC = 1'b0,
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parameter int unsigned RegFileDataWidth = 32,
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parameter int unsigned DmHaltAddr = 32'h1A110800,
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parameter int unsigned DmExceptionAddr = 32'h1A110808
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parameter bit PMPEnable = 1'b0,
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parameter int unsigned PMPGranularity = 0,
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parameter int unsigned PMPNumRegions = 4,
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parameter int unsigned MHPMCounterNum = 0,
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parameter int unsigned MHPMCounterWidth = 40,
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parameter bit RV32E = 1'b0,
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parameter rv32m_e RV32M = RV32MFast,
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parameter rv32b_e RV32B = RV32BNone,
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parameter bit BranchTargetALU = 1'b0,
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parameter bit WritebackStage = 1'b0,
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parameter bit ICache = 1'b0,
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parameter bit ICacheECC = 1'b0,
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parameter int unsigned BusSizeECC = BUS_SIZE,
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parameter int unsigned TagSizeECC = IC_TAG_SIZE,
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parameter int unsigned LineSizeECC = IC_LINE_SIZE,
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parameter bit BranchPredictor = 1'b0,
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parameter bit DbgTriggerEn = 1'b0,
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parameter int unsigned DbgHwBreakNum = 1,
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parameter bit ResetAll = 1'b0,
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parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
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parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
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parameter bit SecureIbex = 1'b0,
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parameter bit DummyInstructions = 1'b0,
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parameter bit RegFileECC = 1'b0,
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parameter int unsigned RegFileDataWidth = 32,
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parameter int unsigned DmHaltAddr = 32'h1A110800,
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parameter int unsigned DmExceptionAddr = 32'h1A110808
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) (
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// Clock and Reset
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input logic clk_i,
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input logic rst_ni,
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// Clock and Reset
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input logic clk_i,
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input logic rst_ni,
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input logic [31:0] hart_id_i,
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input logic [31:0] boot_addr_i,
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input logic [31:0] hart_id_i,
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input logic [31:0] boot_addr_i,
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// Instruction memory interface
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output logic instr_req_o,
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input logic instr_gnt_i,
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input logic instr_rvalid_i,
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output logic [31:0] instr_addr_o,
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input logic [31:0] instr_rdata_i,
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input logic instr_err_i,
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// Instruction memory interface
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output logic instr_req_o,
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input logic instr_gnt_i,
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input logic instr_rvalid_i,
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output logic [31:0] instr_addr_o,
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input logic [31:0] instr_rdata_i,
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input logic instr_err_i,
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// Data memory interface
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output logic data_req_o,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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output logic data_we_o,
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output logic [3:0] data_be_o,
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output logic [31:0] data_addr_o,
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output logic [31:0] data_wdata_o,
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input logic [31:0] data_rdata_i,
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input logic data_err_i,
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// Data memory interface
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output logic data_req_o,
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input logic data_gnt_i,
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input logic data_rvalid_i,
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output logic data_we_o,
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output logic [3:0] data_be_o,
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output logic [31:0] data_addr_o,
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output logic [31:0] data_wdata_o,
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input logic [31:0] data_rdata_i,
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input logic data_err_i,
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// Register file interface
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output logic dummy_instr_id_o,
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output logic [4:0] rf_raddr_a_o,
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output logic [4:0] rf_raddr_b_o,
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output logic [4:0] rf_waddr_wb_o,
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output logic rf_we_wb_o,
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output logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc_o,
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input logic [RegFileDataWidth-1:0] rf_rdata_a_ecc_i,
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input logic [RegFileDataWidth-1:0] rf_rdata_b_ecc_i,
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// Register file interface
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output logic dummy_instr_id_o,
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output logic [4:0] rf_raddr_a_o,
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output logic [4:0] rf_raddr_b_o,
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output logic [4:0] rf_waddr_wb_o,
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output logic rf_we_wb_o,
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output logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc_o,
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input logic [RegFileDataWidth-1:0] rf_rdata_a_ecc_i,
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input logic [RegFileDataWidth-1:0] rf_rdata_b_ecc_i,
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// RAMs interface
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output logic [IC_NUM_WAYS-1:0] ic_tag_req_o,
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output logic ic_tag_write_o,
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output logic [IC_INDEX_W-1:0] ic_tag_addr_o,
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output logic [TagSizeECC-1:0] ic_tag_wdata_o,
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input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
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output logic [IC_NUM_WAYS-1:0] ic_data_req_o,
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output logic ic_data_write_o,
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output logic [IC_INDEX_W-1:0] ic_data_addr_o,
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output logic [LineSizeECC-1:0] ic_data_wdata_o,
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input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
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// RAMs interface
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output logic [IC_NUM_WAYS-1:0] ic_tag_req_o,
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output logic ic_tag_write_o,
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output logic [IC_INDEX_W-1:0] ic_tag_addr_o,
|
||||
output logic [TagSizeECC-1:0] ic_tag_wdata_o,
|
||||
input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
|
||||
output logic [IC_NUM_WAYS-1:0] ic_data_req_o,
|
||||
output logic ic_data_write_o,
|
||||
output logic [IC_INDEX_W-1:0] ic_data_addr_o,
|
||||
output logic [LineSizeECC-1:0] ic_data_wdata_o,
|
||||
input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
|
||||
|
||||
// Interrupt inputs
|
||||
input logic irq_software_i,
|
||||
input logic irq_timer_i,
|
||||
input logic irq_external_i,
|
||||
input logic [14:0] irq_fast_i,
|
||||
input logic irq_nm_i, // non-maskeable interrupt
|
||||
output logic irq_pending_o,
|
||||
// Interrupt inputs
|
||||
input logic irq_software_i,
|
||||
input logic irq_timer_i,
|
||||
input logic irq_external_i,
|
||||
input logic [14:0] irq_fast_i,
|
||||
input logic irq_nm_i, // non-maskeable interrupt
|
||||
output logic irq_pending_o,
|
||||
|
||||
// Debug Interface
|
||||
input logic debug_req_i,
|
||||
output crash_dump_t crash_dump_o,
|
||||
// Debug Interface
|
||||
input logic debug_req_i,
|
||||
output crash_dump_t crash_dump_o,
|
||||
|
||||
// RISC-V Formal Interface
|
||||
// Does not comply with the coding standards of _i/_o suffixes, but follows
|
||||
// the convention of RISC-V Formal Interface Specification.
|
||||
// RISC-V Formal Interface
|
||||
// Does not comply with the coding standards of _i/_o suffixes, but follows
|
||||
// the convention of RISC-V Formal Interface Specification.
|
||||
`ifdef RVFI
|
||||
output logic rvfi_valid,
|
||||
output logic [63:0] rvfi_order,
|
||||
output logic [31:0] rvfi_insn,
|
||||
output logic rvfi_trap,
|
||||
output logic rvfi_halt,
|
||||
output logic rvfi_intr,
|
||||
output logic [ 1:0] rvfi_mode,
|
||||
output logic [ 1:0] rvfi_ixl,
|
||||
output logic [ 4:0] rvfi_rs1_addr,
|
||||
output logic [ 4:0] rvfi_rs2_addr,
|
||||
output logic [ 4:0] rvfi_rs3_addr,
|
||||
output logic [31:0] rvfi_rs1_rdata,
|
||||
output logic [31:0] rvfi_rs2_rdata,
|
||||
output logic [31:0] rvfi_rs3_rdata,
|
||||
output logic [ 4:0] rvfi_rd_addr,
|
||||
output logic [31:0] rvfi_rd_wdata,
|
||||
output logic [31:0] rvfi_pc_rdata,
|
||||
output logic [31:0] rvfi_pc_wdata,
|
||||
output logic [31:0] rvfi_mem_addr,
|
||||
output logic [ 3:0] rvfi_mem_rmask,
|
||||
output logic [ 3:0] rvfi_mem_wmask,
|
||||
output logic [31:0] rvfi_mem_rdata,
|
||||
output logic [31:0] rvfi_mem_wdata,
|
||||
output logic rvfi_valid,
|
||||
output logic [63:0] rvfi_order,
|
||||
output logic [31:0] rvfi_insn,
|
||||
output logic rvfi_trap,
|
||||
output logic rvfi_halt,
|
||||
output logic rvfi_intr,
|
||||
output logic [ 1:0] rvfi_mode,
|
||||
output logic [ 1:0] rvfi_ixl,
|
||||
output logic [ 4:0] rvfi_rs1_addr,
|
||||
output logic [ 4:0] rvfi_rs2_addr,
|
||||
output logic [ 4:0] rvfi_rs3_addr,
|
||||
output logic [31:0] rvfi_rs1_rdata,
|
||||
output logic [31:0] rvfi_rs2_rdata,
|
||||
output logic [31:0] rvfi_rs3_rdata,
|
||||
output logic [ 4:0] rvfi_rd_addr,
|
||||
output logic [31:0] rvfi_rd_wdata,
|
||||
output logic [31:0] rvfi_pc_rdata,
|
||||
output logic [31:0] rvfi_pc_wdata,
|
||||
output logic [31:0] rvfi_mem_addr,
|
||||
output logic [ 3:0] rvfi_mem_rmask,
|
||||
output logic [ 3:0] rvfi_mem_wmask,
|
||||
output logic [31:0] rvfi_mem_rdata,
|
||||
output logic [31:0] rvfi_mem_wdata,
|
||||
`endif
|
||||
|
||||
// CPU Control Signals
|
||||
input logic fetch_enable_i,
|
||||
output logic alert_minor_o,
|
||||
output logic alert_major_o,
|
||||
output logic core_busy_o
|
||||
// CPU Control Signals
|
||||
input logic fetch_enable_i,
|
||||
output logic alert_minor_o,
|
||||
output logic alert_major_o,
|
||||
output logic core_busy_o
|
||||
);
|
||||
|
||||
localparam int unsigned PMP_NUM_CHAN = 2;
|
||||
|
|
|
|||
|
|
@ -13,110 +13,110 @@
|
|||
`include "prim_assert.sv"
|
||||
|
||||
module ibex_cs_registers #(
|
||||
parameter bit DbgTriggerEn = 0,
|
||||
parameter int unsigned DbgHwBreakNum = 1,
|
||||
parameter bit DataIndTiming = 1'b0,
|
||||
parameter bit DummyInstructions = 1'b0,
|
||||
parameter bit ShadowCSR = 1'b0,
|
||||
parameter bit ICache = 1'b0,
|
||||
parameter int unsigned MHPMCounterNum = 10,
|
||||
parameter int unsigned MHPMCounterWidth = 40,
|
||||
parameter bit PMPEnable = 0,
|
||||
parameter int unsigned PMPGranularity = 0,
|
||||
parameter int unsigned PMPNumRegions = 4,
|
||||
parameter bit RV32E = 0,
|
||||
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
|
||||
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone
|
||||
parameter bit DbgTriggerEn = 0,
|
||||
parameter int unsigned DbgHwBreakNum = 1,
|
||||
parameter bit DataIndTiming = 1'b0,
|
||||
parameter bit DummyInstructions = 1'b0,
|
||||
parameter bit ShadowCSR = 1'b0,
|
||||
parameter bit ICache = 1'b0,
|
||||
parameter int unsigned MHPMCounterNum = 10,
|
||||
parameter int unsigned MHPMCounterWidth = 40,
|
||||
parameter bit PMPEnable = 0,
|
||||
parameter int unsigned PMPGranularity = 0,
|
||||
parameter int unsigned PMPNumRegions = 4,
|
||||
parameter bit RV32E = 0,
|
||||
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
|
||||
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone
|
||||
) (
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
// Hart ID
|
||||
input logic [31:0] hart_id_i,
|
||||
// Hart ID
|
||||
input logic [31:0] hart_id_i,
|
||||
|
||||
// Privilege mode
|
||||
output ibex_pkg::priv_lvl_e priv_mode_id_o,
|
||||
output ibex_pkg::priv_lvl_e priv_mode_if_o,
|
||||
output ibex_pkg::priv_lvl_e priv_mode_lsu_o,
|
||||
output logic csr_mstatus_tw_o,
|
||||
// Privilege mode
|
||||
output ibex_pkg::priv_lvl_e priv_mode_id_o,
|
||||
output ibex_pkg::priv_lvl_e priv_mode_if_o,
|
||||
output ibex_pkg::priv_lvl_e priv_mode_lsu_o,
|
||||
output logic csr_mstatus_tw_o,
|
||||
|
||||
// mtvec
|
||||
output logic [31:0] csr_mtvec_o,
|
||||
input logic csr_mtvec_init_i,
|
||||
input logic [31:0] boot_addr_i,
|
||||
// mtvec
|
||||
output logic [31:0] csr_mtvec_o,
|
||||
input logic csr_mtvec_init_i,
|
||||
input logic [31:0] boot_addr_i,
|
||||
|
||||
// Interface to registers (SRAM like)
|
||||
input logic csr_access_i,
|
||||
input ibex_pkg::csr_num_e csr_addr_i,
|
||||
input logic [31:0] csr_wdata_i,
|
||||
input ibex_pkg::csr_op_e csr_op_i,
|
||||
input csr_op_en_i,
|
||||
output logic [31:0] csr_rdata_o,
|
||||
// Interface to registers (SRAM like)
|
||||
input logic csr_access_i,
|
||||
input ibex_pkg::csr_num_e csr_addr_i,
|
||||
input logic [31:0] csr_wdata_i,
|
||||
input ibex_pkg::csr_op_e csr_op_i,
|
||||
input csr_op_en_i,
|
||||
output logic [31:0] csr_rdata_o,
|
||||
|
||||
// interrupts
|
||||
input logic irq_software_i,
|
||||
input logic irq_timer_i,
|
||||
input logic irq_external_i,
|
||||
input logic [14:0] irq_fast_i,
|
||||
input logic nmi_mode_i,
|
||||
output logic irq_pending_o, // interrupt request pending
|
||||
output ibex_pkg::irqs_t irqs_o, // interrupt requests qualified with mie
|
||||
output logic csr_mstatus_mie_o,
|
||||
output logic [31:0] csr_mepc_o,
|
||||
// interrupts
|
||||
input logic irq_software_i,
|
||||
input logic irq_timer_i,
|
||||
input logic irq_external_i,
|
||||
input logic [14:0] irq_fast_i,
|
||||
input logic nmi_mode_i,
|
||||
output logic irq_pending_o, // interrupt request pending
|
||||
output ibex_pkg::irqs_t irqs_o, // interrupt requests qualified with mie
|
||||
output logic csr_mstatus_mie_o,
|
||||
output logic [31:0] csr_mepc_o,
|
||||
|
||||
// PMP
|
||||
output ibex_pkg::pmp_cfg_t csr_pmp_cfg_o [PMPNumRegions],
|
||||
output logic [33:0] csr_pmp_addr_o [PMPNumRegions],
|
||||
output ibex_pkg::pmp_mseccfg_t csr_pmp_mseccfg_o,
|
||||
// PMP
|
||||
output ibex_pkg::pmp_cfg_t csr_pmp_cfg_o [PMPNumRegions],
|
||||
output logic [33:0] csr_pmp_addr_o [PMPNumRegions],
|
||||
output ibex_pkg::pmp_mseccfg_t csr_pmp_mseccfg_o,
|
||||
|
||||
// debug
|
||||
input logic debug_mode_i,
|
||||
input ibex_pkg::dbg_cause_e debug_cause_i,
|
||||
input logic debug_csr_save_i,
|
||||
output logic [31:0] csr_depc_o,
|
||||
output logic debug_single_step_o,
|
||||
output logic debug_ebreakm_o,
|
||||
output logic debug_ebreaku_o,
|
||||
output logic trigger_match_o,
|
||||
// debug
|
||||
input logic debug_mode_i,
|
||||
input ibex_pkg::dbg_cause_e debug_cause_i,
|
||||
input logic debug_csr_save_i,
|
||||
output logic [31:0] csr_depc_o,
|
||||
output logic debug_single_step_o,
|
||||
output logic debug_ebreakm_o,
|
||||
output logic debug_ebreaku_o,
|
||||
output logic trigger_match_o,
|
||||
|
||||
input logic [31:0] pc_if_i,
|
||||
input logic [31:0] pc_id_i,
|
||||
input logic [31:0] pc_wb_i,
|
||||
input logic [31:0] pc_if_i,
|
||||
input logic [31:0] pc_id_i,
|
||||
input logic [31:0] pc_wb_i,
|
||||
|
||||
// CPU control bits
|
||||
output logic data_ind_timing_o,
|
||||
output logic dummy_instr_en_o,
|
||||
output logic [2:0] dummy_instr_mask_o,
|
||||
output logic dummy_instr_seed_en_o,
|
||||
output logic [31:0] dummy_instr_seed_o,
|
||||
output logic icache_enable_o,
|
||||
output logic csr_shadow_err_o,
|
||||
// CPU control bits
|
||||
output logic data_ind_timing_o,
|
||||
output logic dummy_instr_en_o,
|
||||
output logic [2:0] dummy_instr_mask_o,
|
||||
output logic dummy_instr_seed_en_o,
|
||||
output logic [31:0] dummy_instr_seed_o,
|
||||
output logic icache_enable_o,
|
||||
output logic csr_shadow_err_o,
|
||||
|
||||
// Exception save/restore
|
||||
input logic csr_save_if_i,
|
||||
input logic csr_save_id_i,
|
||||
input logic csr_save_wb_i,
|
||||
input logic csr_restore_mret_i,
|
||||
input logic csr_restore_dret_i,
|
||||
input logic csr_save_cause_i,
|
||||
input ibex_pkg::exc_cause_e csr_mcause_i,
|
||||
input logic [31:0] csr_mtval_i,
|
||||
output logic illegal_csr_insn_o, // access to non-existent CSR,
|
||||
// with wrong priviledge level, or
|
||||
// missing write permissions
|
||||
// Performance Counters
|
||||
input logic instr_ret_i, // instr retired in ID/EX stage
|
||||
input logic instr_ret_compressed_i, // compressed instr retired
|
||||
input logic iside_wait_i, // core waiting for the iside
|
||||
input logic jump_i, // jump instr seen (j, jr, jal, jalr)
|
||||
input logic branch_i, // branch instr seen (bf, bnf)
|
||||
input logic branch_taken_i, // branch was taken
|
||||
input logic mem_load_i, // load from memory in this cycle
|
||||
input logic mem_store_i, // store to memory in this cycle
|
||||
input logic dside_wait_i, // core waiting for the dside
|
||||
input logic mul_wait_i, // core waiting for multiply
|
||||
input logic div_wait_i // core waiting for divide
|
||||
// Exception save/restore
|
||||
input logic csr_save_if_i,
|
||||
input logic csr_save_id_i,
|
||||
input logic csr_save_wb_i,
|
||||
input logic csr_restore_mret_i,
|
||||
input logic csr_restore_dret_i,
|
||||
input logic csr_save_cause_i,
|
||||
input ibex_pkg::exc_cause_e csr_mcause_i,
|
||||
input logic [31:0] csr_mtval_i,
|
||||
output logic illegal_csr_insn_o, // access to non-existent CSR,
|
||||
// with wrong priviledge level, or
|
||||
// missing write permissions
|
||||
// Performance Counters
|
||||
input logic instr_ret_i, // instr retired in ID/EX stage
|
||||
input logic instr_ret_compressed_i, // compressed instr retired
|
||||
input logic iside_wait_i, // core waiting for the iside
|
||||
input logic jump_i, // jump instr seen (j, jr, jal, jalr)
|
||||
input logic branch_i, // branch instr seen (bf, bnf)
|
||||
input logic branch_taken_i, // branch was taken
|
||||
input logic mem_load_i, // load from memory in this cycle
|
||||
input logic mem_store_i, // store to memory in this cycle
|
||||
input logic dside_wait_i, // core waiting for the dside
|
||||
input logic mul_wait_i, // core waiting for multiply
|
||||
input logic div_wait_i // core waiting for divide
|
||||
);
|
||||
|
||||
import ibex_pkg::*;
|
||||
|
|
|
|||
|
|
@ -9,18 +9,18 @@
|
|||
`include "prim_assert.sv"
|
||||
|
||||
module ibex_csr #(
|
||||
parameter int unsigned Width = 32,
|
||||
parameter bit ShadowCopy = 1'b0,
|
||||
parameter bit [Width-1:0] ResetValue = '0
|
||||
parameter int unsigned Width = 32,
|
||||
parameter bit ShadowCopy = 1'b0,
|
||||
parameter bit [Width-1:0] ResetValue = '0
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
input logic [Width-1:0] wr_data_i,
|
||||
input logic wr_en_i,
|
||||
output logic [Width-1:0] rd_data_o,
|
||||
input logic [Width-1:0] wr_data_i,
|
||||
input logic wr_en_i,
|
||||
output logic [Width-1:0] rd_data_o,
|
||||
|
||||
output logic rd_error_o
|
||||
output logic rd_error_o
|
||||
);
|
||||
|
||||
logic [Width-1:0] rdata_q;
|
||||
|
|
|
|||
|
|
@ -14,87 +14,87 @@
|
|||
`include "prim_assert.sv"
|
||||
|
||||
module ibex_decoder #(
|
||||
parameter bit RV32E = 0,
|
||||
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
|
||||
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
|
||||
parameter bit BranchTargetALU = 0
|
||||
parameter bit RV32E = 0,
|
||||
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
|
||||
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
|
||||
parameter bit BranchTargetALU = 0
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
// to/from controller
|
||||
output logic illegal_insn_o, // illegal instr encountered
|
||||
output logic ebrk_insn_o, // trap instr encountered
|
||||
output logic mret_insn_o, // return from exception instr
|
||||
// encountered
|
||||
output logic dret_insn_o, // return from debug instr encountered
|
||||
output logic ecall_insn_o, // syscall instr encountered
|
||||
output logic wfi_insn_o, // wait for interrupt instr encountered
|
||||
output logic jump_set_o, // jump taken set signal
|
||||
input logic branch_taken_i, // registered branch decision
|
||||
output logic icache_inval_o,
|
||||
// to/from controller
|
||||
output logic illegal_insn_o, // illegal instr encountered
|
||||
output logic ebrk_insn_o, // trap instr encountered
|
||||
output logic mret_insn_o, // return from exception instr
|
||||
// encountered
|
||||
output logic dret_insn_o, // return from debug instr encountered
|
||||
output logic ecall_insn_o, // syscall instr encountered
|
||||
output logic wfi_insn_o, // wait for interrupt instr encountered
|
||||
output logic jump_set_o, // jump taken set signal
|
||||
input logic branch_taken_i, // registered branch decision
|
||||
output logic icache_inval_o,
|
||||
|
||||
// from IF-ID pipeline register
|
||||
input logic instr_first_cycle_i, // instruction read is in its first cycle
|
||||
input logic [31:0] instr_rdata_i, // instruction read from memory/cache
|
||||
input logic [31:0] instr_rdata_alu_i, // instruction read from memory/cache
|
||||
// replicated to ease fan-out)
|
||||
// from IF-ID pipeline register
|
||||
input logic instr_first_cycle_i, // instruction read is in its first cycle
|
||||
input logic [31:0] instr_rdata_i, // instruction read from memory/cache
|
||||
input logic [31:0] instr_rdata_alu_i, // instruction read from memory/cache
|
||||
// replicated to ease fan-out)
|
||||
|
||||
input logic illegal_c_insn_i, // compressed instruction decode failed
|
||||
input logic illegal_c_insn_i, // compressed instruction decode failed
|
||||
|
||||
// immediates
|
||||
output ibex_pkg::imm_a_sel_e imm_a_mux_sel_o, // immediate selection for operand a
|
||||
output ibex_pkg::imm_b_sel_e imm_b_mux_sel_o, // immediate selection for operand b
|
||||
output ibex_pkg::op_a_sel_e bt_a_mux_sel_o, // branch target selection operand a
|
||||
output ibex_pkg::imm_b_sel_e bt_b_mux_sel_o, // branch target selection operand b
|
||||
output logic [31:0] imm_i_type_o,
|
||||
output logic [31:0] imm_s_type_o,
|
||||
output logic [31:0] imm_b_type_o,
|
||||
output logic [31:0] imm_u_type_o,
|
||||
output logic [31:0] imm_j_type_o,
|
||||
output logic [31:0] zimm_rs1_type_o,
|
||||
// immediates
|
||||
output ibex_pkg::imm_a_sel_e imm_a_mux_sel_o, // immediate selection for operand a
|
||||
output ibex_pkg::imm_b_sel_e imm_b_mux_sel_o, // immediate selection for operand b
|
||||
output ibex_pkg::op_a_sel_e bt_a_mux_sel_o, // branch target selection operand a
|
||||
output ibex_pkg::imm_b_sel_e bt_b_mux_sel_o, // branch target selection operand b
|
||||
output logic [31:0] imm_i_type_o,
|
||||
output logic [31:0] imm_s_type_o,
|
||||
output logic [31:0] imm_b_type_o,
|
||||
output logic [31:0] imm_u_type_o,
|
||||
output logic [31:0] imm_j_type_o,
|
||||
output logic [31:0] zimm_rs1_type_o,
|
||||
|
||||
// register file
|
||||
output ibex_pkg::rf_wd_sel_e rf_wdata_sel_o, // RF write data selection
|
||||
output logic rf_we_o, // write enable for regfile
|
||||
output logic [4:0] rf_raddr_a_o,
|
||||
output logic [4:0] rf_raddr_b_o,
|
||||
output logic [4:0] rf_waddr_o,
|
||||
output logic rf_ren_a_o, // Instruction reads from RF addr A
|
||||
output logic rf_ren_b_o, // Instruction reads from RF addr B
|
||||
// register file
|
||||
output ibex_pkg::rf_wd_sel_e rf_wdata_sel_o, // RF write data selection
|
||||
output logic rf_we_o, // write enable for regfile
|
||||
output logic [4:0] rf_raddr_a_o,
|
||||
output logic [4:0] rf_raddr_b_o,
|
||||
output logic [4:0] rf_waddr_o,
|
||||
output logic rf_ren_a_o, // Instruction reads from RF addr A
|
||||
output logic rf_ren_b_o, // Instruction reads from RF addr B
|
||||
|
||||
// ALU
|
||||
output ibex_pkg::alu_op_e alu_operator_o, // ALU operation selection
|
||||
output ibex_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC,
|
||||
// immediate or zero
|
||||
output ibex_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or
|
||||
// immediate
|
||||
output logic alu_multicycle_o, // ternary bitmanip instruction
|
||||
// ALU
|
||||
output ibex_pkg::alu_op_e alu_operator_o, // ALU operation selection
|
||||
output ibex_pkg::op_a_sel_e alu_op_a_mux_sel_o, // operand a selection: reg value, PC,
|
||||
// immediate or zero
|
||||
output ibex_pkg::op_b_sel_e alu_op_b_mux_sel_o, // operand b selection: reg value or
|
||||
// immediate
|
||||
output logic alu_multicycle_o, // ternary bitmanip instruction
|
||||
|
||||
// MULT & DIV
|
||||
output logic mult_en_o, // perform integer multiplication
|
||||
output logic div_en_o, // perform integer division or remainder
|
||||
output logic mult_sel_o, // as above but static, for data muxes
|
||||
output logic div_sel_o, // as above but static, for data muxes
|
||||
// MULT & DIV
|
||||
output logic mult_en_o, // perform integer multiplication
|
||||
output logic div_en_o, // perform integer division or remainder
|
||||
output logic mult_sel_o, // as above but static, for data muxes
|
||||
output logic div_sel_o, // as above but static, for data muxes
|
||||
|
||||
output ibex_pkg::md_op_e multdiv_operator_o,
|
||||
output logic [1:0] multdiv_signed_mode_o,
|
||||
output ibex_pkg::md_op_e multdiv_operator_o,
|
||||
output logic [1:0] multdiv_signed_mode_o,
|
||||
|
||||
// CSRs
|
||||
output logic csr_access_o, // access to CSR
|
||||
output ibex_pkg::csr_op_e csr_op_o, // operation to perform on CSR
|
||||
// CSRs
|
||||
output logic csr_access_o, // access to CSR
|
||||
output ibex_pkg::csr_op_e csr_op_o, // operation to perform on CSR
|
||||
|
||||
// LSU
|
||||
output logic data_req_o, // start transaction to data memory
|
||||
output logic data_we_o, // write enable
|
||||
output logic [1:0] data_type_o, // size of transaction: byte, half
|
||||
// word or word
|
||||
output logic data_sign_extension_o, // sign extension for data read from
|
||||
// memory
|
||||
// LSU
|
||||
output logic data_req_o, // start transaction to data memory
|
||||
output logic data_we_o, // write enable
|
||||
output logic [1:0] data_type_o, // size of transaction: byte, half
|
||||
// word or word
|
||||
output logic data_sign_extension_o, // sign extension for data read from
|
||||
// memory
|
||||
|
||||
// jump/branches
|
||||
output logic jump_in_dec_o, // jump is being calculated in ALU
|
||||
output logic branch_in_dec_o
|
||||
// jump/branches
|
||||
output logic jump_in_dec_o, // jump is being calculated in ALU
|
||||
output logic branch_in_dec_o
|
||||
);
|
||||
|
||||
import ibex_pkg::*;
|
||||
|
|
|
|||
|
|
@ -12,21 +12,21 @@ module ibex_dummy_instr import ibex_pkg::*; #(
|
|||
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
|
||||
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault
|
||||
) (
|
||||
// Clock and reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
// Clock and reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
// Interface to CSRs
|
||||
input logic dummy_instr_en_i,
|
||||
input logic [2:0] dummy_instr_mask_i,
|
||||
input logic dummy_instr_seed_en_i,
|
||||
input logic [31:0] dummy_instr_seed_i,
|
||||
// Interface to CSRs
|
||||
input logic dummy_instr_en_i,
|
||||
input logic [2:0] dummy_instr_mask_i,
|
||||
input logic dummy_instr_seed_en_i,
|
||||
input logic [31:0] dummy_instr_seed_i,
|
||||
|
||||
// Interface to IF stage
|
||||
input logic fetch_valid_i,
|
||||
input logic id_in_ready_i,
|
||||
output logic insert_dummy_instr_o,
|
||||
output logic [31:0] dummy_instr_data_o
|
||||
// Interface to IF stage
|
||||
input logic fetch_valid_i,
|
||||
input logic id_in_ready_i,
|
||||
output logic insert_dummy_instr_o,
|
||||
output logic [31:0] dummy_instr_data_o
|
||||
);
|
||||
|
||||
localparam int unsigned TIMEOUT_CNT_W = 5;
|
||||
|
|
|
|||
|
|
@ -9,48 +9,48 @@
|
|||
* Execution block: Hosts ALU and MUL/DIV unit
|
||||
*/
|
||||
module ibex_ex_block #(
|
||||
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
|
||||
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
|
||||
parameter bit BranchTargetALU = 0
|
||||
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
|
||||
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
|
||||
parameter bit BranchTargetALU = 0
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
// ALU
|
||||
input ibex_pkg::alu_op_e alu_operator_i,
|
||||
input logic [31:0] alu_operand_a_i,
|
||||
input logic [31:0] alu_operand_b_i,
|
||||
input logic alu_instr_first_cycle_i,
|
||||
// ALU
|
||||
input ibex_pkg::alu_op_e alu_operator_i,
|
||||
input logic [31:0] alu_operand_a_i,
|
||||
input logic [31:0] alu_operand_b_i,
|
||||
input logic alu_instr_first_cycle_i,
|
||||
|
||||
// Branch Target ALU
|
||||
// All of these signals are unusued when BranchTargetALU == 0
|
||||
input logic [31:0] bt_a_operand_i,
|
||||
input logic [31:0] bt_b_operand_i,
|
||||
// Branch Target ALU
|
||||
// All of these signals are unusued when BranchTargetALU == 0
|
||||
input logic [31:0] bt_a_operand_i,
|
||||
input logic [31:0] bt_b_operand_i,
|
||||
|
||||
// Multiplier/Divider
|
||||
input ibex_pkg::md_op_e multdiv_operator_i,
|
||||
input logic mult_en_i, // dynamic enable signal, for FSM control
|
||||
input logic div_en_i, // dynamic enable signal, for FSM control
|
||||
input logic mult_sel_i, // static decoder output, for data muxes
|
||||
input logic div_sel_i, // static decoder output, for data muxes
|
||||
input logic [1:0] multdiv_signed_mode_i,
|
||||
input logic [31:0] multdiv_operand_a_i,
|
||||
input logic [31:0] multdiv_operand_b_i,
|
||||
input logic multdiv_ready_id_i,
|
||||
input logic data_ind_timing_i,
|
||||
// Multiplier/Divider
|
||||
input ibex_pkg::md_op_e multdiv_operator_i,
|
||||
input logic mult_en_i, // dynamic enable signal, for FSM control
|
||||
input logic div_en_i, // dynamic enable signal, for FSM control
|
||||
input logic mult_sel_i, // static decoder output, for data muxes
|
||||
input logic div_sel_i, // static decoder output, for data muxes
|
||||
input logic [1:0] multdiv_signed_mode_i,
|
||||
input logic [31:0] multdiv_operand_a_i,
|
||||
input logic [31:0] multdiv_operand_b_i,
|
||||
input logic multdiv_ready_id_i,
|
||||
input logic data_ind_timing_i,
|
||||
|
||||
// intermediate val reg
|
||||
output logic [1:0] imd_val_we_o,
|
||||
output logic [33:0] imd_val_d_o[2],
|
||||
input logic [33:0] imd_val_q_i[2],
|
||||
// intermediate val reg
|
||||
output logic [1:0] imd_val_we_o,
|
||||
output logic [33:0] imd_val_d_o[2],
|
||||
input logic [33:0] imd_val_q_i[2],
|
||||
|
||||
// Outputs
|
||||
output logic [31:0] alu_adder_result_ex_o, // to LSU
|
||||
output logic [31:0] result_ex_o,
|
||||
output logic [31:0] branch_target_o, // to IF
|
||||
output logic branch_decision_o, // to ID
|
||||
// Outputs
|
||||
output logic [31:0] alu_adder_result_ex_o, // to LSU
|
||||
output logic [31:0] result_ex_o,
|
||||
output logic [31:0] branch_target_o, // to IF
|
||||
output logic branch_decision_o, // to ID
|
||||
|
||||
output logic ex_valid_o // EX has valid output
|
||||
output logic ex_valid_o // EX has valid output
|
||||
);
|
||||
|
||||
import ibex_pkg::*;
|
||||
|
|
|
|||
|
|
@ -16,27 +16,27 @@ module ibex_fetch_fifo #(
|
|||
parameter int unsigned NUM_REQS = 2,
|
||||
parameter bit ResetAll = 1'b0
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
// control signals
|
||||
input logic clear_i, // clears the contents of the FIFO
|
||||
output logic [NUM_REQS-1:0] busy_o,
|
||||
// control signals
|
||||
input logic clear_i, // clears the contents of the FIFO
|
||||
output logic [NUM_REQS-1:0] busy_o,
|
||||
|
||||
// input port
|
||||
input logic in_valid_i,
|
||||
input logic [31:0] in_addr_i,
|
||||
input logic [31:0] in_rdata_i,
|
||||
input logic in_err_i,
|
||||
// input port
|
||||
input logic in_valid_i,
|
||||
input logic [31:0] in_addr_i,
|
||||
input logic [31:0] in_rdata_i,
|
||||
input logic in_err_i,
|
||||
|
||||
// output port
|
||||
output logic out_valid_o,
|
||||
input logic out_ready_i,
|
||||
output logic [31:0] out_addr_o,
|
||||
output logic [31:0] out_addr_next_o,
|
||||
output logic [31:0] out_rdata_o,
|
||||
output logic out_err_o,
|
||||
output logic out_err_plus2_o
|
||||
// output port
|
||||
output logic out_valid_o,
|
||||
input logic out_ready_i,
|
||||
output logic [31:0] out_addr_o,
|
||||
output logic [31:0] out_addr_next_o,
|
||||
output logic [31:0] out_rdata_o,
|
||||
output logic out_err_o,
|
||||
output logic out_err_plus2_o
|
||||
);
|
||||
|
||||
localparam int unsigned DEPTH = NUM_REQS+1;
|
||||
|
|
|
|||
|
|
@ -20,53 +20,53 @@ module ibex_icache import ibex_pkg::*; #(
|
|||
// Only cache branch targets
|
||||
parameter bit BranchCache = 1'b0
|
||||
) (
|
||||
// Clock and reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
// Clock and reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
// Signal that the core would like instructions
|
||||
input logic req_i,
|
||||
// Signal that the core would like instructions
|
||||
input logic req_i,
|
||||
|
||||
// Set the cache's address counter
|
||||
input logic branch_i,
|
||||
input logic branch_spec_i,
|
||||
input logic predicted_branch_i,
|
||||
input logic branch_mispredict_i,
|
||||
input logic [31:0] addr_i,
|
||||
// Set the cache's address counter
|
||||
input logic branch_i,
|
||||
input logic branch_spec_i,
|
||||
input logic predicted_branch_i,
|
||||
input logic branch_mispredict_i,
|
||||
input logic [31:0] addr_i,
|
||||
|
||||
// IF stage interface: Pass fetched instructions to the core
|
||||
input logic ready_i,
|
||||
output logic valid_o,
|
||||
output logic [31:0] rdata_o,
|
||||
output logic [31:0] addr_o,
|
||||
output logic err_o,
|
||||
output logic err_plus2_o,
|
||||
// IF stage interface: Pass fetched instructions to the core
|
||||
input logic ready_i,
|
||||
output logic valid_o,
|
||||
output logic [31:0] rdata_o,
|
||||
output logic [31:0] addr_o,
|
||||
output logic err_o,
|
||||
output logic err_plus2_o,
|
||||
|
||||
// Instruction memory / interconnect interface: Fetch instruction data from memory
|
||||
output logic instr_req_o,
|
||||
input logic instr_gnt_i,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic [BUS_SIZE-1:0] instr_rdata_i,
|
||||
input logic instr_err_i,
|
||||
input logic instr_pmp_err_i,
|
||||
input logic instr_rvalid_i,
|
||||
// Instruction memory / interconnect interface: Fetch instruction data from memory
|
||||
output logic instr_req_o,
|
||||
input logic instr_gnt_i,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic [BUS_SIZE-1:0] instr_rdata_i,
|
||||
input logic instr_err_i,
|
||||
input logic instr_pmp_err_i,
|
||||
input logic instr_rvalid_i,
|
||||
|
||||
// RAM IO
|
||||
output logic [IC_NUM_WAYS-1:0] ic_tag_req_o,
|
||||
output logic ic_tag_write_o,
|
||||
output logic [IC_INDEX_W-1:0] ic_tag_addr_o,
|
||||
output logic [TagSizeECC-1:0] ic_tag_wdata_o,
|
||||
input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
|
||||
output logic [IC_NUM_WAYS-1:0] ic_data_req_o,
|
||||
output logic ic_data_write_o,
|
||||
output logic [IC_INDEX_W-1:0] ic_data_addr_o,
|
||||
output logic [LineSizeECC-1:0] ic_data_wdata_o,
|
||||
input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
|
||||
// RAM IO
|
||||
output logic [IC_NUM_WAYS-1:0] ic_tag_req_o,
|
||||
output logic ic_tag_write_o,
|
||||
output logic [IC_INDEX_W-1:0] ic_tag_addr_o,
|
||||
output logic [TagSizeECC-1:0] ic_tag_wdata_o,
|
||||
input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
|
||||
output logic [IC_NUM_WAYS-1:0] ic_data_req_o,
|
||||
output logic ic_data_write_o,
|
||||
output logic [IC_INDEX_W-1:0] ic_data_addr_o,
|
||||
output logic [LineSizeECC-1:0] ic_data_wdata_o,
|
||||
input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
|
||||
|
||||
// Cache status
|
||||
input logic icache_enable_i,
|
||||
input logic icache_inval_i,
|
||||
output logic busy_o
|
||||
// Cache status
|
||||
input logic icache_enable_i,
|
||||
input logic icache_inval_i,
|
||||
output logic busy_o
|
||||
);
|
||||
|
||||
// Number of fill buffers (must be >= 2)
|
||||
|
|
|
|||
|
|
@ -18,170 +18,170 @@
|
|||
`include "dv_fcov_macros.svh"
|
||||
|
||||
module ibex_id_stage #(
|
||||
parameter bit RV32E = 0,
|
||||
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
|
||||
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
|
||||
parameter bit DataIndTiming = 1'b0,
|
||||
parameter bit BranchTargetALU = 0,
|
||||
parameter bit SpecBranch = 0,
|
||||
parameter bit WritebackStage = 0,
|
||||
parameter bit BranchPredictor = 0
|
||||
parameter bit RV32E = 0,
|
||||
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast,
|
||||
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone,
|
||||
parameter bit DataIndTiming = 1'b0,
|
||||
parameter bit BranchTargetALU = 0,
|
||||
parameter bit SpecBranch = 0,
|
||||
parameter bit WritebackStage = 0,
|
||||
parameter bit BranchPredictor = 0
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
output logic ctrl_busy_o,
|
||||
output logic illegal_insn_o,
|
||||
output logic ctrl_busy_o,
|
||||
output logic illegal_insn_o,
|
||||
|
||||
// Interface to IF stage
|
||||
input logic instr_valid_i,
|
||||
input logic [31:0] instr_rdata_i, // from IF-ID pipeline registers
|
||||
input logic [31:0] instr_rdata_alu_i, // from IF-ID pipeline registers
|
||||
input logic [15:0] instr_rdata_c_i, // from IF-ID pipeline registers
|
||||
input logic instr_is_compressed_i,
|
||||
input logic instr_bp_taken_i,
|
||||
output logic instr_req_o,
|
||||
output logic instr_first_cycle_id_o,
|
||||
output logic instr_valid_clear_o, // kill instr in IF-ID reg
|
||||
output logic id_in_ready_o, // ID stage is ready for next instr
|
||||
output logic icache_inval_o,
|
||||
// Interface to IF stage
|
||||
input logic instr_valid_i,
|
||||
input logic [31:0] instr_rdata_i, // from IF-ID pipeline registers
|
||||
input logic [31:0] instr_rdata_alu_i, // from IF-ID pipeline registers
|
||||
input logic [15:0] instr_rdata_c_i, // from IF-ID pipeline registers
|
||||
input logic instr_is_compressed_i,
|
||||
input logic instr_bp_taken_i,
|
||||
output logic instr_req_o,
|
||||
output logic instr_first_cycle_id_o,
|
||||
output logic instr_valid_clear_o, // kill instr in IF-ID reg
|
||||
output logic id_in_ready_o, // ID stage is ready for next instr
|
||||
output logic icache_inval_o,
|
||||
|
||||
// Jumps and branches
|
||||
input logic branch_decision_i,
|
||||
// Jumps and branches
|
||||
input logic branch_decision_i,
|
||||
|
||||
// IF and ID stage signals
|
||||
output logic pc_set_o,
|
||||
output logic pc_set_spec_o,
|
||||
output ibex_pkg::pc_sel_e pc_mux_o,
|
||||
output logic nt_branch_mispredict_o,
|
||||
output ibex_pkg::exc_pc_sel_e exc_pc_mux_o,
|
||||
output ibex_pkg::exc_cause_e exc_cause_o,
|
||||
// IF and ID stage signals
|
||||
output logic pc_set_o,
|
||||
output logic pc_set_spec_o,
|
||||
output ibex_pkg::pc_sel_e pc_mux_o,
|
||||
output logic nt_branch_mispredict_o,
|
||||
output ibex_pkg::exc_pc_sel_e exc_pc_mux_o,
|
||||
output ibex_pkg::exc_cause_e exc_cause_o,
|
||||
|
||||
input logic illegal_c_insn_i,
|
||||
input logic instr_fetch_err_i,
|
||||
input logic instr_fetch_err_plus2_i,
|
||||
input logic illegal_c_insn_i,
|
||||
input logic instr_fetch_err_i,
|
||||
input logic instr_fetch_err_plus2_i,
|
||||
|
||||
input logic [31:0] pc_id_i,
|
||||
input logic [31:0] pc_id_i,
|
||||
|
||||
// Stalls
|
||||
input logic ex_valid_i, // EX stage has valid output
|
||||
input logic lsu_resp_valid_i, // LSU has valid output, or is done
|
||||
// ALU
|
||||
output ibex_pkg::alu_op_e alu_operator_ex_o,
|
||||
output logic [31:0] alu_operand_a_ex_o,
|
||||
output logic [31:0] alu_operand_b_ex_o,
|
||||
// Stalls
|
||||
input logic ex_valid_i, // EX stage has valid output
|
||||
input logic lsu_resp_valid_i, // LSU has valid output, or is done
|
||||
// ALU
|
||||
output ibex_pkg::alu_op_e alu_operator_ex_o,
|
||||
output logic [31:0] alu_operand_a_ex_o,
|
||||
output logic [31:0] alu_operand_b_ex_o,
|
||||
|
||||
// Multicycle Operation Stage Register
|
||||
input logic [1:0] imd_val_we_ex_i,
|
||||
input logic [33:0] imd_val_d_ex_i[2],
|
||||
output logic [33:0] imd_val_q_ex_o[2],
|
||||
// Multicycle Operation Stage Register
|
||||
input logic [1:0] imd_val_we_ex_i,
|
||||
input logic [33:0] imd_val_d_ex_i[2],
|
||||
output logic [33:0] imd_val_q_ex_o[2],
|
||||
|
||||
// Branch target ALU
|
||||
output logic [31:0] bt_a_operand_o,
|
||||
output logic [31:0] bt_b_operand_o,
|
||||
// Branch target ALU
|
||||
output logic [31:0] bt_a_operand_o,
|
||||
output logic [31:0] bt_b_operand_o,
|
||||
|
||||
// MUL, DIV
|
||||
output logic mult_en_ex_o,
|
||||
output logic div_en_ex_o,
|
||||
output logic mult_sel_ex_o,
|
||||
output logic div_sel_ex_o,
|
||||
output ibex_pkg::md_op_e multdiv_operator_ex_o,
|
||||
output logic [1:0] multdiv_signed_mode_ex_o,
|
||||
output logic [31:0] multdiv_operand_a_ex_o,
|
||||
output logic [31:0] multdiv_operand_b_ex_o,
|
||||
output logic multdiv_ready_id_o,
|
||||
// MUL, DIV
|
||||
output logic mult_en_ex_o,
|
||||
output logic div_en_ex_o,
|
||||
output logic mult_sel_ex_o,
|
||||
output logic div_sel_ex_o,
|
||||
output ibex_pkg::md_op_e multdiv_operator_ex_o,
|
||||
output logic [1:0] multdiv_signed_mode_ex_o,
|
||||
output logic [31:0] multdiv_operand_a_ex_o,
|
||||
output logic [31:0] multdiv_operand_b_ex_o,
|
||||
output logic multdiv_ready_id_o,
|
||||
|
||||
// CSR
|
||||
output logic csr_access_o,
|
||||
output ibex_pkg::csr_op_e csr_op_o,
|
||||
output logic csr_op_en_o,
|
||||
output logic csr_save_if_o,
|
||||
output logic csr_save_id_o,
|
||||
output logic csr_save_wb_o,
|
||||
output logic csr_restore_mret_id_o,
|
||||
output logic csr_restore_dret_id_o,
|
||||
output logic csr_save_cause_o,
|
||||
output logic [31:0] csr_mtval_o,
|
||||
input ibex_pkg::priv_lvl_e priv_mode_i,
|
||||
input logic csr_mstatus_tw_i,
|
||||
input logic illegal_csr_insn_i,
|
||||
input logic data_ind_timing_i,
|
||||
// CSR
|
||||
output logic csr_access_o,
|
||||
output ibex_pkg::csr_op_e csr_op_o,
|
||||
output logic csr_op_en_o,
|
||||
output logic csr_save_if_o,
|
||||
output logic csr_save_id_o,
|
||||
output logic csr_save_wb_o,
|
||||
output logic csr_restore_mret_id_o,
|
||||
output logic csr_restore_dret_id_o,
|
||||
output logic csr_save_cause_o,
|
||||
output logic [31:0] csr_mtval_o,
|
||||
input ibex_pkg::priv_lvl_e priv_mode_i,
|
||||
input logic csr_mstatus_tw_i,
|
||||
input logic illegal_csr_insn_i,
|
||||
input logic data_ind_timing_i,
|
||||
|
||||
// Interface to load store unit
|
||||
output logic lsu_req_o,
|
||||
output logic lsu_we_o,
|
||||
output logic [1:0] lsu_type_o,
|
||||
output logic lsu_sign_ext_o,
|
||||
output logic [31:0] lsu_wdata_o,
|
||||
// Interface to load store unit
|
||||
output logic lsu_req_o,
|
||||
output logic lsu_we_o,
|
||||
output logic [1:0] lsu_type_o,
|
||||
output logic lsu_sign_ext_o,
|
||||
output logic [31:0] lsu_wdata_o,
|
||||
|
||||
input logic lsu_req_done_i, // Data req to LSU is complete and
|
||||
// instruction can move to writeback
|
||||
// (only relevant where writeback stage is
|
||||
// present)
|
||||
input logic lsu_req_done_i, // Data req to LSU is complete and
|
||||
// instruction can move to writeback
|
||||
// (only relevant where writeback stage is
|
||||
// present)
|
||||
|
||||
input logic lsu_addr_incr_req_i,
|
||||
input logic [31:0] lsu_addr_last_i,
|
||||
input logic lsu_addr_incr_req_i,
|
||||
input logic [31:0] lsu_addr_last_i,
|
||||
|
||||
// Interrupt signals
|
||||
input logic csr_mstatus_mie_i,
|
||||
input logic irq_pending_i,
|
||||
input ibex_pkg::irqs_t irqs_i,
|
||||
input logic irq_nm_i,
|
||||
output logic nmi_mode_o,
|
||||
// Interrupt signals
|
||||
input logic csr_mstatus_mie_i,
|
||||
input logic irq_pending_i,
|
||||
input ibex_pkg::irqs_t irqs_i,
|
||||
input logic irq_nm_i,
|
||||
output logic nmi_mode_o,
|
||||
|
||||
input logic lsu_load_err_i,
|
||||
input logic lsu_store_err_i,
|
||||
input logic lsu_load_err_i,
|
||||
input logic lsu_store_err_i,
|
||||
|
||||
// Debug Signal
|
||||
output logic debug_mode_o,
|
||||
output ibex_pkg::dbg_cause_e debug_cause_o,
|
||||
output logic debug_csr_save_o,
|
||||
input logic debug_req_i,
|
||||
input logic debug_single_step_i,
|
||||
input logic debug_ebreakm_i,
|
||||
input logic debug_ebreaku_i,
|
||||
input logic trigger_match_i,
|
||||
// Debug Signal
|
||||
output logic debug_mode_o,
|
||||
output ibex_pkg::dbg_cause_e debug_cause_o,
|
||||
output logic debug_csr_save_o,
|
||||
input logic debug_req_i,
|
||||
input logic debug_single_step_i,
|
||||
input logic debug_ebreakm_i,
|
||||
input logic debug_ebreaku_i,
|
||||
input logic trigger_match_i,
|
||||
|
||||
// Write back signal
|
||||
input logic [31:0] result_ex_i,
|
||||
input logic [31:0] csr_rdata_i,
|
||||
// Write back signal
|
||||
input logic [31:0] result_ex_i,
|
||||
input logic [31:0] csr_rdata_i,
|
||||
|
||||
// Register file read
|
||||
output logic [4:0] rf_raddr_a_o,
|
||||
input logic [31:0] rf_rdata_a_i,
|
||||
output logic [4:0] rf_raddr_b_o,
|
||||
input logic [31:0] rf_rdata_b_i,
|
||||
output logic rf_ren_a_o,
|
||||
output logic rf_ren_b_o,
|
||||
// Register file read
|
||||
output logic [4:0] rf_raddr_a_o,
|
||||
input logic [31:0] rf_rdata_a_i,
|
||||
output logic [4:0] rf_raddr_b_o,
|
||||
input logic [31:0] rf_rdata_b_i,
|
||||
output logic rf_ren_a_o,
|
||||
output logic rf_ren_b_o,
|
||||
|
||||
// Register file write (via writeback)
|
||||
output logic [4:0] rf_waddr_id_o,
|
||||
output logic [31:0] rf_wdata_id_o,
|
||||
output logic rf_we_id_o,
|
||||
output logic rf_rd_a_wb_match_o,
|
||||
output logic rf_rd_b_wb_match_o,
|
||||
// Register file write (via writeback)
|
||||
output logic [4:0] rf_waddr_id_o,
|
||||
output logic [31:0] rf_wdata_id_o,
|
||||
output logic rf_we_id_o,
|
||||
output logic rf_rd_a_wb_match_o,
|
||||
output logic rf_rd_b_wb_match_o,
|
||||
|
||||
// Register write information from writeback (for resolving data hazards)
|
||||
input logic [4:0] rf_waddr_wb_i,
|
||||
input logic [31:0] rf_wdata_fwd_wb_i,
|
||||
input logic rf_write_wb_i,
|
||||
// Register write information from writeback (for resolving data hazards)
|
||||
input logic [4:0] rf_waddr_wb_i,
|
||||
input logic [31:0] rf_wdata_fwd_wb_i,
|
||||
input logic rf_write_wb_i,
|
||||
|
||||
output logic en_wb_o,
|
||||
output ibex_pkg::wb_instr_type_e instr_type_wb_o,
|
||||
output logic instr_perf_count_id_o,
|
||||
input logic ready_wb_i,
|
||||
input logic outstanding_load_wb_i,
|
||||
input logic outstanding_store_wb_i,
|
||||
output logic en_wb_o,
|
||||
output ibex_pkg::wb_instr_type_e instr_type_wb_o,
|
||||
output logic instr_perf_count_id_o,
|
||||
input logic ready_wb_i,
|
||||
input logic outstanding_load_wb_i,
|
||||
input logic outstanding_store_wb_i,
|
||||
|
||||
// Performance Counters
|
||||
output logic perf_jump_o, // executing a jump instr
|
||||
output logic perf_branch_o, // executing a branch instr
|
||||
output logic perf_tbranch_o, // executing a taken branch instr
|
||||
output logic perf_dside_wait_o, // instruction in ID/EX is awaiting memory
|
||||
// access to finish before proceeding
|
||||
output logic perf_mul_wait_o,
|
||||
output logic perf_div_wait_o,
|
||||
output logic instr_id_done_o
|
||||
// Performance Counters
|
||||
output logic perf_jump_o, // executing a jump instr
|
||||
output logic perf_branch_o, // executing a branch instr
|
||||
output logic perf_tbranch_o, // executing a taken branch instr
|
||||
output logic perf_dside_wait_o, // instruction in ID/EX is awaiting memory
|
||||
// access to finish before proceeding
|
||||
output logic perf_mul_wait_o,
|
||||
output logic perf_div_wait_o,
|
||||
output logic instr_id_done_o
|
||||
);
|
||||
|
||||
import ibex_pkg::*;
|
||||
|
|
|
|||
|
|
@ -13,102 +13,102 @@
|
|||
`include "prim_assert.sv"
|
||||
|
||||
module ibex_if_stage import ibex_pkg::*; #(
|
||||
parameter int unsigned DmHaltAddr = 32'h1A110800,
|
||||
parameter int unsigned DmExceptionAddr = 32'h1A110808,
|
||||
parameter bit DummyInstructions = 1'b0,
|
||||
parameter bit ICache = 1'b0,
|
||||
parameter bit ICacheECC = 1'b0,
|
||||
parameter int unsigned BusSizeECC = BUS_SIZE,
|
||||
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
|
||||
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
|
||||
parameter bit PCIncrCheck = 1'b0,
|
||||
parameter bit ResetAll = 1'b0,
|
||||
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
|
||||
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
|
||||
parameter bit BranchPredictor = 1'b0
|
||||
parameter int unsigned DmHaltAddr = 32'h1A110800,
|
||||
parameter int unsigned DmExceptionAddr = 32'h1A110808,
|
||||
parameter bit DummyInstructions = 1'b0,
|
||||
parameter bit ICache = 1'b0,
|
||||
parameter bit ICacheECC = 1'b0,
|
||||
parameter int unsigned BusSizeECC = BUS_SIZE,
|
||||
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
|
||||
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
|
||||
parameter bit PCIncrCheck = 1'b0,
|
||||
parameter bit ResetAll = 1'b0,
|
||||
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
|
||||
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
|
||||
parameter bit BranchPredictor = 1'b0
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
input logic [31:0] boot_addr_i, // also used for mtvec
|
||||
input logic req_i, // instruction request control
|
||||
input logic [31:0] boot_addr_i, // also used for mtvec
|
||||
input logic req_i, // instruction request control
|
||||
|
||||
// instruction cache interface
|
||||
output logic instr_req_o,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic instr_gnt_i,
|
||||
input logic instr_rvalid_i,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic instr_err_i,
|
||||
input logic instr_pmp_err_i,
|
||||
// instruction cache interface
|
||||
output logic instr_req_o,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic instr_gnt_i,
|
||||
input logic instr_rvalid_i,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic instr_err_i,
|
||||
input logic instr_pmp_err_i,
|
||||
|
||||
// ICache RAM IO
|
||||
output logic [IC_NUM_WAYS-1:0] ic_tag_req_o,
|
||||
output logic ic_tag_write_o,
|
||||
output logic [IC_INDEX_W-1:0] ic_tag_addr_o,
|
||||
output logic [TagSizeECC-1:0] ic_tag_wdata_o,
|
||||
input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
|
||||
output logic [IC_NUM_WAYS-1:0] ic_data_req_o,
|
||||
output logic ic_data_write_o,
|
||||
output logic [IC_INDEX_W-1:0] ic_data_addr_o,
|
||||
output logic [LineSizeECC-1:0] ic_data_wdata_o,
|
||||
input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
|
||||
// ICache RAM IO
|
||||
output logic [IC_NUM_WAYS-1:0] ic_tag_req_o,
|
||||
output logic ic_tag_write_o,
|
||||
output logic [IC_INDEX_W-1:0] ic_tag_addr_o,
|
||||
output logic [TagSizeECC-1:0] ic_tag_wdata_o,
|
||||
input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
|
||||
output logic [IC_NUM_WAYS-1:0] ic_data_req_o,
|
||||
output logic ic_data_write_o,
|
||||
output logic [IC_INDEX_W-1:0] ic_data_addr_o,
|
||||
output logic [LineSizeECC-1:0] ic_data_wdata_o,
|
||||
input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
|
||||
|
||||
// output of ID stage
|
||||
output logic instr_valid_id_o, // instr in IF-ID is valid
|
||||
output logic instr_new_id_o, // instr in IF-ID is new
|
||||
output logic [31:0] instr_rdata_id_o, // instr for ID stage
|
||||
output logic [31:0] instr_rdata_alu_id_o, // replicated instr for ID stage
|
||||
// to reduce fan-out
|
||||
output logic [15:0] instr_rdata_c_id_o, // compressed instr for ID stage
|
||||
// (mtval), meaningful only if
|
||||
// instr_is_compressed_id_o = 1'b1
|
||||
output logic instr_is_compressed_id_o, // compressed decoder thinks this
|
||||
// is a compressed instr
|
||||
output logic instr_bp_taken_o, // instruction was predicted to be
|
||||
// a taken branch
|
||||
output logic instr_fetch_err_o, // bus error on fetch
|
||||
output logic instr_fetch_err_plus2_o, // bus error misaligned
|
||||
output logic illegal_c_insn_id_o, // compressed decoder thinks this
|
||||
// is an invalid instr
|
||||
output logic dummy_instr_id_o, // Instruction is a dummy
|
||||
output logic [31:0] pc_if_o,
|
||||
output logic [31:0] pc_id_o,
|
||||
// output of ID stage
|
||||
output logic instr_valid_id_o, // instr in IF-ID is valid
|
||||
output logic instr_new_id_o, // instr in IF-ID is new
|
||||
output logic [31:0] instr_rdata_id_o, // instr for ID stage
|
||||
output logic [31:0] instr_rdata_alu_id_o, // replicated instr for ID stage
|
||||
// to reduce fan-out
|
||||
output logic [15:0] instr_rdata_c_id_o, // compressed instr for ID stage
|
||||
// (mtval), meaningful only if
|
||||
// instr_is_compressed_id_o = 1'b1
|
||||
output logic instr_is_compressed_id_o, // compressed decoder thinks this
|
||||
// is a compressed instr
|
||||
output logic instr_bp_taken_o, // instruction was predicted to be
|
||||
// a taken branch
|
||||
output logic instr_fetch_err_o, // bus error on fetch
|
||||
output logic instr_fetch_err_plus2_o, // bus error misaligned
|
||||
output logic illegal_c_insn_id_o, // compressed decoder thinks this
|
||||
// is an invalid instr
|
||||
output logic dummy_instr_id_o, // Instruction is a dummy
|
||||
output logic [31:0] pc_if_o,
|
||||
output logic [31:0] pc_id_o,
|
||||
|
||||
// control signals
|
||||
input logic instr_valid_clear_i, // clear instr valid bit in IF-ID
|
||||
input logic pc_set_i, // set the PC to a new value
|
||||
input logic pc_set_spec_i,
|
||||
input pc_sel_e pc_mux_i, // selector for PC multiplexer
|
||||
input logic nt_branch_mispredict_i, // Not-taken branch in ID/EX was
|
||||
// mispredicted (predicted taken)
|
||||
input exc_pc_sel_e exc_pc_mux_i, // selects ISR address
|
||||
input exc_cause_e exc_cause, // selects ISR address for
|
||||
// vectorized interrupt lines
|
||||
input logic dummy_instr_en_i,
|
||||
input logic [2:0] dummy_instr_mask_i,
|
||||
input logic dummy_instr_seed_en_i,
|
||||
input logic [31:0] dummy_instr_seed_i,
|
||||
input logic icache_enable_i,
|
||||
input logic icache_inval_i,
|
||||
// control signals
|
||||
input logic instr_valid_clear_i, // clear instr valid bit in IF-ID
|
||||
input logic pc_set_i, // set the PC to a new value
|
||||
input logic pc_set_spec_i,
|
||||
input pc_sel_e pc_mux_i, // selector for PC multiplexer
|
||||
input logic nt_branch_mispredict_i, // Not-taken branch in ID/EX was
|
||||
// mispredicted (predicted taken)
|
||||
input exc_pc_sel_e exc_pc_mux_i, // selects ISR address
|
||||
input exc_cause_e exc_cause, // selects ISR address for
|
||||
// vectorized interrupt lines
|
||||
input logic dummy_instr_en_i,
|
||||
input logic [2:0] dummy_instr_mask_i,
|
||||
input logic dummy_instr_seed_en_i,
|
||||
input logic [31:0] dummy_instr_seed_i,
|
||||
input logic icache_enable_i,
|
||||
input logic icache_inval_i,
|
||||
|
||||
// jump and branch target
|
||||
input logic [31:0] branch_target_ex_i, // branch/jump target address
|
||||
// jump and branch target
|
||||
input logic [31:0] branch_target_ex_i, // branch/jump target address
|
||||
|
||||
// CSRs
|
||||
input logic [31:0] csr_mepc_i, // PC to restore after handling
|
||||
// the interrupt/exception
|
||||
input logic [31:0] csr_depc_i, // PC to restore after handling
|
||||
// the debug request
|
||||
input logic [31:0] csr_mtvec_i, // base PC to jump to on exception
|
||||
output logic csr_mtvec_init_o, // tell CS regfile to init mtvec
|
||||
// CSRs
|
||||
input logic [31:0] csr_mepc_i, // PC to restore after handling
|
||||
// the interrupt/exception
|
||||
input logic [31:0] csr_depc_i, // PC to restore after handling
|
||||
// the debug request
|
||||
input logic [31:0] csr_mtvec_i, // base PC to jump to on exception
|
||||
output logic csr_mtvec_init_o, // tell CS regfile to init mtvec
|
||||
|
||||
// pipeline stall
|
||||
input logic id_in_ready_i, // ID stage is ready for new instr
|
||||
// pipeline stall
|
||||
input logic id_in_ready_i, // ID stage is ready for new instr
|
||||
|
||||
// misc signals
|
||||
output logic pc_mismatch_alert_o,
|
||||
output logic if_busy_o // IF stage is busy fetching instr
|
||||
// misc signals
|
||||
output logic pc_mismatch_alert_o,
|
||||
output logic if_busy_o // IF stage is busy fetching instr
|
||||
);
|
||||
|
||||
logic instr_valid_id_d, instr_valid_id_q;
|
||||
|
|
|
|||
|
|
@ -16,54 +16,54 @@
|
|||
|
||||
module ibex_load_store_unit
|
||||
(
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
// data interface
|
||||
output logic data_req_o,
|
||||
input logic data_gnt_i,
|
||||
input logic data_rvalid_i,
|
||||
input logic data_err_i,
|
||||
input logic data_pmp_err_i,
|
||||
// data interface
|
||||
output logic data_req_o,
|
||||
input logic data_gnt_i,
|
||||
input logic data_rvalid_i,
|
||||
input logic data_err_i,
|
||||
input logic data_pmp_err_i,
|
||||
|
||||
output logic [31:0] data_addr_o,
|
||||
output logic data_we_o,
|
||||
output logic [3:0] data_be_o,
|
||||
output logic [31:0] data_wdata_o,
|
||||
input logic [31:0] data_rdata_i,
|
||||
output logic [31:0] data_addr_o,
|
||||
output logic data_we_o,
|
||||
output logic [3:0] data_be_o,
|
||||
output logic [31:0] data_wdata_o,
|
||||
input logic [31:0] data_rdata_i,
|
||||
|
||||
// signals to/from ID/EX stage
|
||||
input logic lsu_we_i, // write enable -> from ID/EX
|
||||
input logic [1:0] lsu_type_i, // data type: word, half word, byte -> from ID/EX
|
||||
input logic [31:0] lsu_wdata_i, // data to write to memory -> from ID/EX
|
||||
input logic lsu_sign_ext_i, // sign extension -> from ID/EX
|
||||
// signals to/from ID/EX stage
|
||||
input logic lsu_we_i, // write enable -> from ID/EX
|
||||
input logic [1:0] lsu_type_i, // data type: word, half word, byte -> from ID/EX
|
||||
input logic [31:0] lsu_wdata_i, // data to write to memory -> from ID/EX
|
||||
input logic lsu_sign_ext_i, // sign extension -> from ID/EX
|
||||
|
||||
output logic [31:0] lsu_rdata_o, // requested data -> to ID/EX
|
||||
output logic lsu_rdata_valid_o,
|
||||
input logic lsu_req_i, // data request -> from ID/EX
|
||||
output logic [31:0] lsu_rdata_o, // requested data -> to ID/EX
|
||||
output logic lsu_rdata_valid_o,
|
||||
input logic lsu_req_i, // data request -> from ID/EX
|
||||
|
||||
input logic [31:0] adder_result_ex_i, // address computed in ALU -> from ID/EX
|
||||
input logic [31:0] adder_result_ex_i, // address computed in ALU -> from ID/EX
|
||||
|
||||
output logic addr_incr_req_o, // request address increment for
|
||||
// misaligned accesses -> to ID/EX
|
||||
output logic [31:0] addr_last_o, // address of last transaction -> to controller
|
||||
// -> mtval
|
||||
// -> AGU for misaligned accesses
|
||||
output logic addr_incr_req_o, // request address increment for
|
||||
// misaligned accesses -> to ID/EX
|
||||
output logic [31:0] addr_last_o, // address of last transaction -> to controller
|
||||
// -> mtval
|
||||
// -> AGU for misaligned accesses
|
||||
|
||||
output logic lsu_req_done_o, // Signals that data request is complete
|
||||
// (only need to await final data
|
||||
// response) -> to ID/EX
|
||||
output logic lsu_req_done_o, // Signals that data request is complete
|
||||
// (only need to await final data
|
||||
// response) -> to ID/EX
|
||||
|
||||
output logic lsu_resp_valid_o, // LSU has response from transaction -> to ID/EX
|
||||
output logic lsu_resp_valid_o, // LSU has response from transaction -> to ID/EX
|
||||
|
||||
// exception signals
|
||||
output logic load_err_o,
|
||||
output logic store_err_o,
|
||||
// exception signals
|
||||
output logic load_err_o,
|
||||
output logic store_err_o,
|
||||
|
||||
output logic busy_o,
|
||||
output logic busy_o,
|
||||
|
||||
output logic perf_load_o,
|
||||
output logic perf_store_o
|
||||
output logic perf_load_o,
|
||||
output logic perf_store_o
|
||||
);
|
||||
|
||||
logic [31:0] data_addr;
|
||||
|
|
|
|||
|
|
@ -7,97 +7,97 @@
|
|||
// those from the main core. The second core runs synchronously with the main core, delayed by
|
||||
// LockstepOffset cycles.
|
||||
module ibex_lockstep import ibex_pkg::*; #(
|
||||
parameter int unsigned LockstepOffset = 2,
|
||||
parameter bit PMPEnable = 1'b0,
|
||||
parameter int unsigned PMPGranularity = 0,
|
||||
parameter int unsigned PMPNumRegions = 4,
|
||||
parameter int unsigned MHPMCounterNum = 0,
|
||||
parameter int unsigned MHPMCounterWidth = 40,
|
||||
parameter bit RV32E = 1'b0,
|
||||
parameter rv32m_e RV32M = RV32MFast,
|
||||
parameter rv32b_e RV32B = RV32BNone,
|
||||
parameter bit BranchTargetALU = 1'b0,
|
||||
parameter bit WritebackStage = 1'b0,
|
||||
parameter bit ICache = 1'b0,
|
||||
parameter bit ICacheECC = 1'b0,
|
||||
parameter int unsigned BusSizeECC = BUS_SIZE,
|
||||
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
|
||||
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
|
||||
parameter bit BranchPredictor = 1'b0,
|
||||
parameter bit DbgTriggerEn = 1'b0,
|
||||
parameter int unsigned DbgHwBreakNum = 1,
|
||||
parameter bit ResetAll = 1'b0,
|
||||
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
|
||||
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
|
||||
parameter bit SecureIbex = 1'b0,
|
||||
parameter bit DummyInstructions = 1'b0,
|
||||
parameter bit RegFileECC = 1'b0,
|
||||
parameter int unsigned RegFileDataWidth = 32,
|
||||
parameter int unsigned DmHaltAddr = 32'h1A110800,
|
||||
parameter int unsigned DmExceptionAddr = 32'h1A110808
|
||||
parameter int unsigned LockstepOffset = 2,
|
||||
parameter bit PMPEnable = 1'b0,
|
||||
parameter int unsigned PMPGranularity = 0,
|
||||
parameter int unsigned PMPNumRegions = 4,
|
||||
parameter int unsigned MHPMCounterNum = 0,
|
||||
parameter int unsigned MHPMCounterWidth = 40,
|
||||
parameter bit RV32E = 1'b0,
|
||||
parameter rv32m_e RV32M = RV32MFast,
|
||||
parameter rv32b_e RV32B = RV32BNone,
|
||||
parameter bit BranchTargetALU = 1'b0,
|
||||
parameter bit WritebackStage = 1'b0,
|
||||
parameter bit ICache = 1'b0,
|
||||
parameter bit ICacheECC = 1'b0,
|
||||
parameter int unsigned BusSizeECC = BUS_SIZE,
|
||||
parameter int unsigned TagSizeECC = IC_TAG_SIZE,
|
||||
parameter int unsigned LineSizeECC = IC_LINE_SIZE,
|
||||
parameter bit BranchPredictor = 1'b0,
|
||||
parameter bit DbgTriggerEn = 1'b0,
|
||||
parameter int unsigned DbgHwBreakNum = 1,
|
||||
parameter bit ResetAll = 1'b0,
|
||||
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
|
||||
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
|
||||
parameter bit SecureIbex = 1'b0,
|
||||
parameter bit DummyInstructions = 1'b0,
|
||||
parameter bit RegFileECC = 1'b0,
|
||||
parameter int unsigned RegFileDataWidth = 32,
|
||||
parameter int unsigned DmHaltAddr = 32'h1A110800,
|
||||
parameter int unsigned DmExceptionAddr = 32'h1A110808
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
input logic [31:0] hart_id_i,
|
||||
input logic [31:0] boot_addr_i,
|
||||
input logic [31:0] hart_id_i,
|
||||
input logic [31:0] boot_addr_i,
|
||||
|
||||
input logic instr_req_i,
|
||||
input logic instr_gnt_i,
|
||||
input logic instr_rvalid_i,
|
||||
input logic [31:0] instr_addr_i,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic [6:0] instr_rdata_intg_i,
|
||||
input logic instr_err_i,
|
||||
input logic instr_req_i,
|
||||
input logic instr_gnt_i,
|
||||
input logic instr_rvalid_i,
|
||||
input logic [31:0] instr_addr_i,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic [6:0] instr_rdata_intg_i,
|
||||
input logic instr_err_i,
|
||||
|
||||
input logic data_req_i,
|
||||
input logic data_gnt_i,
|
||||
input logic data_rvalid_i,
|
||||
input logic data_we_i,
|
||||
input logic [3:0] data_be_i,
|
||||
input logic [31:0] data_addr_i,
|
||||
input logic [31:0] data_wdata_i,
|
||||
output logic [6:0] data_wdata_intg_o,
|
||||
input logic [31:0] data_rdata_i,
|
||||
input logic [6:0] data_rdata_intg_i,
|
||||
input logic data_err_i,
|
||||
input logic data_req_i,
|
||||
input logic data_gnt_i,
|
||||
input logic data_rvalid_i,
|
||||
input logic data_we_i,
|
||||
input logic [3:0] data_be_i,
|
||||
input logic [31:0] data_addr_i,
|
||||
input logic [31:0] data_wdata_i,
|
||||
output logic [6:0] data_wdata_intg_o,
|
||||
input logic [31:0] data_rdata_i,
|
||||
input logic [6:0] data_rdata_intg_i,
|
||||
input logic data_err_i,
|
||||
|
||||
input logic dummy_instr_id_i,
|
||||
input logic [4:0] rf_raddr_a_i,
|
||||
input logic [4:0] rf_raddr_b_i,
|
||||
input logic [4:0] rf_waddr_wb_i,
|
||||
input logic rf_we_wb_i,
|
||||
input logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc_i,
|
||||
input logic [RegFileDataWidth-1:0] rf_rdata_a_ecc_i,
|
||||
input logic [RegFileDataWidth-1:0] rf_rdata_b_ecc_i,
|
||||
input logic dummy_instr_id_i,
|
||||
input logic [4:0] rf_raddr_a_i,
|
||||
input logic [4:0] rf_raddr_b_i,
|
||||
input logic [4:0] rf_waddr_wb_i,
|
||||
input logic rf_we_wb_i,
|
||||
input logic [RegFileDataWidth-1:0] rf_wdata_wb_ecc_i,
|
||||
input logic [RegFileDataWidth-1:0] rf_rdata_a_ecc_i,
|
||||
input logic [RegFileDataWidth-1:0] rf_rdata_b_ecc_i,
|
||||
|
||||
input logic [IC_NUM_WAYS-1:0] ic_tag_req_i,
|
||||
input logic ic_tag_write_i,
|
||||
input logic [IC_INDEX_W-1:0] ic_tag_addr_i,
|
||||
input logic [TagSizeECC-1:0] ic_tag_wdata_i,
|
||||
input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
|
||||
input logic [IC_NUM_WAYS-1:0] ic_data_req_i,
|
||||
input logic ic_data_write_i,
|
||||
input logic [IC_INDEX_W-1:0] ic_data_addr_i,
|
||||
input logic [LineSizeECC-1:0] ic_data_wdata_i,
|
||||
input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
|
||||
input logic [IC_NUM_WAYS-1:0] ic_tag_req_i,
|
||||
input logic ic_tag_write_i,
|
||||
input logic [IC_INDEX_W-1:0] ic_tag_addr_i,
|
||||
input logic [TagSizeECC-1:0] ic_tag_wdata_i,
|
||||
input logic [TagSizeECC-1:0] ic_tag_rdata_i [IC_NUM_WAYS],
|
||||
input logic [IC_NUM_WAYS-1:0] ic_data_req_i,
|
||||
input logic ic_data_write_i,
|
||||
input logic [IC_INDEX_W-1:0] ic_data_addr_i,
|
||||
input logic [LineSizeECC-1:0] ic_data_wdata_i,
|
||||
input logic [LineSizeECC-1:0] ic_data_rdata_i [IC_NUM_WAYS],
|
||||
|
||||
input logic irq_software_i,
|
||||
input logic irq_timer_i,
|
||||
input logic irq_external_i,
|
||||
input logic [14:0] irq_fast_i,
|
||||
input logic irq_nm_i,
|
||||
input logic irq_pending_i,
|
||||
input logic irq_software_i,
|
||||
input logic irq_timer_i,
|
||||
input logic irq_external_i,
|
||||
input logic [14:0] irq_fast_i,
|
||||
input logic irq_nm_i,
|
||||
input logic irq_pending_i,
|
||||
|
||||
input logic debug_req_i,
|
||||
input crash_dump_t crash_dump_i,
|
||||
input logic debug_req_i,
|
||||
input crash_dump_t crash_dump_i,
|
||||
|
||||
input logic fetch_enable_i,
|
||||
output logic alert_minor_o,
|
||||
output logic alert_major_o,
|
||||
input logic core_busy_i,
|
||||
input logic test_en_i,
|
||||
input logic scan_rst_ni
|
||||
input logic fetch_enable_i,
|
||||
output logic alert_minor_o,
|
||||
output logic alert_major_o,
|
||||
input logic core_busy_i,
|
||||
input logic test_en_i,
|
||||
input logic scan_rst_ni
|
||||
);
|
||||
|
||||
localparam int unsigned LockstepOffsetW = $clog2(LockstepOffset);
|
||||
|
|
|
|||
|
|
@ -15,34 +15,34 @@
|
|||
`include "prim_assert.sv"
|
||||
|
||||
module ibex_multdiv_fast #(
|
||||
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast
|
||||
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MFast
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic mult_en_i, // dynamic enable signal, for FSM control
|
||||
input logic div_en_i, // dynamic enable signal, for FSM control
|
||||
input logic mult_sel_i, // static decoder output, for data muxes
|
||||
input logic div_sel_i, // static decoder output, for data muxes
|
||||
input ibex_pkg::md_op_e operator_i,
|
||||
input logic [1:0] signed_mode_i,
|
||||
input logic [31:0] op_a_i,
|
||||
input logic [31:0] op_b_i,
|
||||
input logic [33:0] alu_adder_ext_i,
|
||||
input logic [31:0] alu_adder_i,
|
||||
input logic equal_to_zero_i,
|
||||
input logic data_ind_timing_i,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic mult_en_i, // dynamic enable signal, for FSM control
|
||||
input logic div_en_i, // dynamic enable signal, for FSM control
|
||||
input logic mult_sel_i, // static decoder output, for data muxes
|
||||
input logic div_sel_i, // static decoder output, for data muxes
|
||||
input ibex_pkg::md_op_e operator_i,
|
||||
input logic [1:0] signed_mode_i,
|
||||
input logic [31:0] op_a_i,
|
||||
input logic [31:0] op_b_i,
|
||||
input logic [33:0] alu_adder_ext_i,
|
||||
input logic [31:0] alu_adder_i,
|
||||
input logic equal_to_zero_i,
|
||||
input logic data_ind_timing_i,
|
||||
|
||||
output logic [32:0] alu_operand_a_o,
|
||||
output logic [32:0] alu_operand_b_o,
|
||||
output logic [32:0] alu_operand_a_o,
|
||||
output logic [32:0] alu_operand_b_o,
|
||||
|
||||
input logic [33:0] imd_val_q_i[2],
|
||||
output logic [33:0] imd_val_d_o[2],
|
||||
output logic [1:0] imd_val_we_o,
|
||||
input logic [33:0] imd_val_q_i[2],
|
||||
output logic [33:0] imd_val_d_o[2],
|
||||
output logic [1:0] imd_val_we_o,
|
||||
|
||||
input logic multdiv_ready_id_i,
|
||||
input logic multdiv_ready_id_i,
|
||||
|
||||
output logic [31:0] multdiv_result_o,
|
||||
output logic valid_o
|
||||
output logic [31:0] multdiv_result_o,
|
||||
output logic valid_o
|
||||
);
|
||||
|
||||
import ibex_pkg::*;
|
||||
|
|
|
|||
|
|
@ -13,33 +13,33 @@
|
|||
|
||||
module ibex_multdiv_slow
|
||||
(
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic mult_en_i, // dynamic enable signal, for FSM control
|
||||
input logic div_en_i, // dynamic enable signal, for FSM control
|
||||
input logic mult_sel_i, // static decoder output, for data muxes
|
||||
input logic div_sel_i, // static decoder output, for data muxes
|
||||
input ibex_pkg::md_op_e operator_i,
|
||||
input logic [1:0] signed_mode_i,
|
||||
input logic [31:0] op_a_i,
|
||||
input logic [31:0] op_b_i,
|
||||
input logic [33:0] alu_adder_ext_i,
|
||||
input logic [31:0] alu_adder_i,
|
||||
input logic equal_to_zero_i,
|
||||
input logic data_ind_timing_i,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic mult_en_i, // dynamic enable signal, for FSM control
|
||||
input logic div_en_i, // dynamic enable signal, for FSM control
|
||||
input logic mult_sel_i, // static decoder output, for data muxes
|
||||
input logic div_sel_i, // static decoder output, for data muxes
|
||||
input ibex_pkg::md_op_e operator_i,
|
||||
input logic [1:0] signed_mode_i,
|
||||
input logic [31:0] op_a_i,
|
||||
input logic [31:0] op_b_i,
|
||||
input logic [33:0] alu_adder_ext_i,
|
||||
input logic [31:0] alu_adder_i,
|
||||
input logic equal_to_zero_i,
|
||||
input logic data_ind_timing_i,
|
||||
|
||||
output logic [32:0] alu_operand_a_o,
|
||||
output logic [32:0] alu_operand_b_o,
|
||||
output logic [32:0] alu_operand_a_o,
|
||||
output logic [32:0] alu_operand_b_o,
|
||||
|
||||
input logic [33:0] imd_val_q_i[2],
|
||||
output logic [33:0] imd_val_d_o[2],
|
||||
output logic [1:0] imd_val_we_o,
|
||||
input logic [33:0] imd_val_q_i[2],
|
||||
output logic [33:0] imd_val_d_o[2],
|
||||
output logic [1:0] imd_val_we_o,
|
||||
|
||||
input logic multdiv_ready_id_i,
|
||||
input logic multdiv_ready_id_i,
|
||||
|
||||
output logic [31:0] multdiv_result_o,
|
||||
output logic [31:0] multdiv_result_o,
|
||||
|
||||
output logic valid_o
|
||||
output logic valid_o
|
||||
);
|
||||
|
||||
import ibex_pkg::*;
|
||||
|
|
|
|||
|
|
@ -3,28 +3,28 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
module ibex_pmp #(
|
||||
// Granularity of NAPOT access,
|
||||
// 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.
|
||||
parameter int unsigned PMPGranularity = 0,
|
||||
// Number of access channels (e.g. i-side + d-side)
|
||||
parameter int unsigned PMPNumChan = 2,
|
||||
// Number of implemented regions
|
||||
parameter int unsigned PMPNumRegions = 4
|
||||
// Granularity of NAPOT access,
|
||||
// 0 = No restriction, 1 = 8 byte, 2 = 16 byte, 3 = 32 byte, etc.
|
||||
parameter int unsigned PMPGranularity = 0,
|
||||
// Number of access channels (e.g. i-side + d-side)
|
||||
parameter int unsigned PMPNumChan = 2,
|
||||
// Number of implemented regions
|
||||
parameter int unsigned PMPNumRegions = 4
|
||||
) (
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
// Interface to CSRs
|
||||
input ibex_pkg::pmp_cfg_t csr_pmp_cfg_i [PMPNumRegions],
|
||||
input logic [33:0] csr_pmp_addr_i [PMPNumRegions],
|
||||
input ibex_pkg::pmp_mseccfg_t csr_pmp_mseccfg_i,
|
||||
// Interface to CSRs
|
||||
input ibex_pkg::pmp_cfg_t csr_pmp_cfg_i [PMPNumRegions],
|
||||
input logic [33:0] csr_pmp_addr_i [PMPNumRegions],
|
||||
input ibex_pkg::pmp_mseccfg_t csr_pmp_mseccfg_i,
|
||||
|
||||
input ibex_pkg::priv_lvl_e priv_mode_i [PMPNumChan],
|
||||
// Access checking channels
|
||||
input logic [33:0] pmp_req_addr_i [PMPNumChan],
|
||||
input ibex_pkg::pmp_req_e pmp_req_type_i [PMPNumChan],
|
||||
output logic pmp_req_err_o [PMPNumChan]
|
||||
input ibex_pkg::priv_lvl_e priv_mode_i [PMPNumChan],
|
||||
// Access checking channels
|
||||
input logic [33:0] pmp_req_addr_i [PMPNumChan],
|
||||
input ibex_pkg::pmp_req_e pmp_req_type_i [PMPNumChan],
|
||||
output logic pmp_req_err_o [PMPNumChan]
|
||||
|
||||
);
|
||||
|
||||
|
|
|
|||
|
|
@ -13,37 +13,37 @@ module ibex_prefetch_buffer #(
|
|||
parameter bit BranchPredictor = 1'b0,
|
||||
parameter bit ResetAll = 1'b0
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
input logic req_i,
|
||||
input logic req_i,
|
||||
|
||||
input logic branch_i,
|
||||
input logic branch_spec_i,
|
||||
input logic predicted_branch_i,
|
||||
input logic branch_mispredict_i,
|
||||
input logic [31:0] addr_i,
|
||||
input logic branch_i,
|
||||
input logic branch_spec_i,
|
||||
input logic predicted_branch_i,
|
||||
input logic branch_mispredict_i,
|
||||
input logic [31:0] addr_i,
|
||||
|
||||
|
||||
input logic ready_i,
|
||||
output logic valid_o,
|
||||
output logic [31:0] rdata_o,
|
||||
output logic [31:0] addr_o,
|
||||
output logic err_o,
|
||||
output logic err_plus2_o,
|
||||
input logic ready_i,
|
||||
output logic valid_o,
|
||||
output logic [31:0] rdata_o,
|
||||
output logic [31:0] addr_o,
|
||||
output logic err_o,
|
||||
output logic err_plus2_o,
|
||||
|
||||
|
||||
// goes to instruction memory / instruction cache
|
||||
output logic instr_req_o,
|
||||
input logic instr_gnt_i,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic instr_err_i,
|
||||
input logic instr_pmp_err_i,
|
||||
input logic instr_rvalid_i,
|
||||
// goes to instruction memory / instruction cache
|
||||
output logic instr_req_o,
|
||||
input logic instr_gnt_i,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic instr_err_i,
|
||||
input logic instr_pmp_err_i,
|
||||
input logic instr_rvalid_i,
|
||||
|
||||
// Prefetch Buffer Status
|
||||
output logic busy_o
|
||||
// Prefetch Buffer Status
|
||||
output logic busy_o
|
||||
);
|
||||
|
||||
localparam int unsigned NUM_REQS = 2;
|
||||
|
|
|
|||
|
|
@ -11,30 +11,30 @@
|
|||
* targeting FPGA synthesis or Verilator simulation.
|
||||
*/
|
||||
module ibex_register_file_ff #(
|
||||
parameter bit RV32E = 0,
|
||||
parameter int unsigned DataWidth = 32,
|
||||
parameter bit DummyInstructions = 0
|
||||
parameter bit RV32E = 0,
|
||||
parameter int unsigned DataWidth = 32,
|
||||
parameter bit DummyInstructions = 0
|
||||
) (
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
input logic test_en_i,
|
||||
input logic dummy_instr_id_i,
|
||||
input logic test_en_i,
|
||||
input logic dummy_instr_id_i,
|
||||
|
||||
//Read port R1
|
||||
input logic [4:0] raddr_a_i,
|
||||
output logic [DataWidth-1:0] rdata_a_o,
|
||||
//Read port R1
|
||||
input logic [4:0] raddr_a_i,
|
||||
output logic [DataWidth-1:0] rdata_a_o,
|
||||
|
||||
//Read port R2
|
||||
input logic [4:0] raddr_b_i,
|
||||
output logic [DataWidth-1:0] rdata_b_o,
|
||||
//Read port R2
|
||||
input logic [4:0] raddr_b_i,
|
||||
output logic [DataWidth-1:0] rdata_b_o,
|
||||
|
||||
|
||||
// Write port W1
|
||||
input logic [4:0] waddr_a_i,
|
||||
input logic [DataWidth-1:0] wdata_a_i,
|
||||
input logic we_a_i
|
||||
// Write port W1
|
||||
input logic [4:0] waddr_a_i,
|
||||
input logic [DataWidth-1:0] wdata_a_i,
|
||||
input logic we_a_i
|
||||
|
||||
);
|
||||
|
||||
|
|
|
|||
|
|
@ -12,29 +12,29 @@
|
|||
* register file when targeting ASIC synthesis or event-based simulators.
|
||||
*/
|
||||
module ibex_register_file_latch #(
|
||||
parameter bit RV32E = 0,
|
||||
parameter int unsigned DataWidth = 32,
|
||||
parameter bit DummyInstructions = 0
|
||||
parameter bit RV32E = 0,
|
||||
parameter int unsigned DataWidth = 32,
|
||||
parameter bit DummyInstructions = 0
|
||||
) (
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
input logic test_en_i,
|
||||
input logic dummy_instr_id_i,
|
||||
input logic test_en_i,
|
||||
input logic dummy_instr_id_i,
|
||||
|
||||
//Read port R1
|
||||
input logic [4:0] raddr_a_i,
|
||||
output logic [DataWidth-1:0] rdata_a_o,
|
||||
//Read port R1
|
||||
input logic [4:0] raddr_a_i,
|
||||
output logic [DataWidth-1:0] rdata_a_o,
|
||||
|
||||
//Read port R2
|
||||
input logic [4:0] raddr_b_i,
|
||||
output logic [DataWidth-1:0] rdata_b_o,
|
||||
//Read port R2
|
||||
input logic [4:0] raddr_b_i,
|
||||
output logic [DataWidth-1:0] rdata_b_o,
|
||||
|
||||
// Write port W1
|
||||
input logic [4:0] waddr_a_i,
|
||||
input logic [DataWidth-1:0] wdata_a_i,
|
||||
input logic we_a_i
|
||||
// Write port W1
|
||||
input logic [4:0] waddr_a_i,
|
||||
input logic [DataWidth-1:0] wdata_a_i,
|
||||
input logic we_a_i
|
||||
|
||||
);
|
||||
|
||||
|
|
|
|||
180
rtl/ibex_top.sv
180
rtl/ibex_top.sv
|
|
@ -13,108 +13,108 @@
|
|||
* Top level module of the ibex RISC-V core
|
||||
*/
|
||||
module ibex_top import ibex_pkg::*; #(
|
||||
parameter bit PMPEnable = 1'b0,
|
||||
parameter int unsigned PMPGranularity = 0,
|
||||
parameter int unsigned PMPNumRegions = 4,
|
||||
parameter int unsigned MHPMCounterNum = 0,
|
||||
parameter int unsigned MHPMCounterWidth = 40,
|
||||
parameter bit RV32E = 1'b0,
|
||||
parameter rv32m_e RV32M = RV32MFast,
|
||||
parameter rv32b_e RV32B = RV32BNone,
|
||||
parameter regfile_e RegFile = RegFileFF,
|
||||
parameter bit BranchTargetALU = 1'b0,
|
||||
parameter bit WritebackStage = 1'b0,
|
||||
parameter bit ICache = 1'b0,
|
||||
parameter bit ICacheECC = 1'b0,
|
||||
parameter bit BranchPredictor = 1'b0,
|
||||
parameter bit DbgTriggerEn = 1'b0,
|
||||
parameter int unsigned DbgHwBreakNum = 1,
|
||||
parameter bit SecureIbex = 1'b0,
|
||||
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
|
||||
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
|
||||
parameter int unsigned DmHaltAddr = 32'h1A110800,
|
||||
parameter int unsigned DmExceptionAddr = 32'h1A110808
|
||||
parameter bit PMPEnable = 1'b0,
|
||||
parameter int unsigned PMPGranularity = 0,
|
||||
parameter int unsigned PMPNumRegions = 4,
|
||||
parameter int unsigned MHPMCounterNum = 0,
|
||||
parameter int unsigned MHPMCounterWidth = 40,
|
||||
parameter bit RV32E = 1'b0,
|
||||
parameter rv32m_e RV32M = RV32MFast,
|
||||
parameter rv32b_e RV32B = RV32BNone,
|
||||
parameter regfile_e RegFile = RegFileFF,
|
||||
parameter bit BranchTargetALU = 1'b0,
|
||||
parameter bit WritebackStage = 1'b0,
|
||||
parameter bit ICache = 1'b0,
|
||||
parameter bit ICacheECC = 1'b0,
|
||||
parameter bit BranchPredictor = 1'b0,
|
||||
parameter bit DbgTriggerEn = 1'b0,
|
||||
parameter int unsigned DbgHwBreakNum = 1,
|
||||
parameter bit SecureIbex = 1'b0,
|
||||
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
|
||||
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
|
||||
parameter int unsigned DmHaltAddr = 32'h1A110800,
|
||||
parameter int unsigned DmExceptionAddr = 32'h1A110808
|
||||
) (
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
input logic test_en_i, // enable all clock gates for testing
|
||||
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
|
||||
input logic test_en_i, // enable all clock gates for testing
|
||||
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
|
||||
|
||||
input logic [31:0] hart_id_i,
|
||||
input logic [31:0] boot_addr_i,
|
||||
input logic [31:0] hart_id_i,
|
||||
input logic [31:0] boot_addr_i,
|
||||
|
||||
// Instruction memory interface
|
||||
output logic instr_req_o,
|
||||
input logic instr_gnt_i,
|
||||
input logic instr_rvalid_i,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic [6:0] instr_rdata_intg_i,
|
||||
input logic instr_err_i,
|
||||
// Instruction memory interface
|
||||
output logic instr_req_o,
|
||||
input logic instr_gnt_i,
|
||||
input logic instr_rvalid_i,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic [6:0] instr_rdata_intg_i,
|
||||
input logic instr_err_i,
|
||||
|
||||
// Data memory interface
|
||||
output logic data_req_o,
|
||||
input logic data_gnt_i,
|
||||
input logic data_rvalid_i,
|
||||
output logic data_we_o,
|
||||
output logic [3:0] data_be_o,
|
||||
output logic [31:0] data_addr_o,
|
||||
output logic [31:0] data_wdata_o,
|
||||
output logic [6:0] data_wdata_intg_o,
|
||||
input logic [31:0] data_rdata_i,
|
||||
input logic [6:0] data_rdata_intg_i,
|
||||
input logic data_err_i,
|
||||
// Data memory interface
|
||||
output logic data_req_o,
|
||||
input logic data_gnt_i,
|
||||
input logic data_rvalid_i,
|
||||
output logic data_we_o,
|
||||
output logic [3:0] data_be_o,
|
||||
output logic [31:0] data_addr_o,
|
||||
output logic [31:0] data_wdata_o,
|
||||
output logic [6:0] data_wdata_intg_o,
|
||||
input logic [31:0] data_rdata_i,
|
||||
input logic [6:0] data_rdata_intg_i,
|
||||
input logic data_err_i,
|
||||
|
||||
// Interrupt inputs
|
||||
input logic irq_software_i,
|
||||
input logic irq_timer_i,
|
||||
input logic irq_external_i,
|
||||
input logic [14:0] irq_fast_i,
|
||||
input logic irq_nm_i, // non-maskeable interrupt
|
||||
// Interrupt inputs
|
||||
input logic irq_software_i,
|
||||
input logic irq_timer_i,
|
||||
input logic irq_external_i,
|
||||
input logic [14:0] irq_fast_i,
|
||||
input logic irq_nm_i, // non-maskeable interrupt
|
||||
|
||||
// Debug Interface
|
||||
input logic debug_req_i,
|
||||
output crash_dump_t crash_dump_o,
|
||||
// Debug Interface
|
||||
input logic debug_req_i,
|
||||
output crash_dump_t crash_dump_o,
|
||||
|
||||
// RISC-V Formal Interface
|
||||
// Does not comply with the coding standards of _i/_o suffixes, but follows
|
||||
// the convention of RISC-V Formal Interface Specification.
|
||||
// RISC-V Formal Interface
|
||||
// Does not comply with the coding standards of _i/_o suffixes, but follows
|
||||
// the convention of RISC-V Formal Interface Specification.
|
||||
`ifdef RVFI
|
||||
output logic rvfi_valid,
|
||||
output logic [63:0] rvfi_order,
|
||||
output logic [31:0] rvfi_insn,
|
||||
output logic rvfi_trap,
|
||||
output logic rvfi_halt,
|
||||
output logic rvfi_intr,
|
||||
output logic [ 1:0] rvfi_mode,
|
||||
output logic [ 1:0] rvfi_ixl,
|
||||
output logic [ 4:0] rvfi_rs1_addr,
|
||||
output logic [ 4:0] rvfi_rs2_addr,
|
||||
output logic [ 4:0] rvfi_rs3_addr,
|
||||
output logic [31:0] rvfi_rs1_rdata,
|
||||
output logic [31:0] rvfi_rs2_rdata,
|
||||
output logic [31:0] rvfi_rs3_rdata,
|
||||
output logic [ 4:0] rvfi_rd_addr,
|
||||
output logic [31:0] rvfi_rd_wdata,
|
||||
output logic [31:0] rvfi_pc_rdata,
|
||||
output logic [31:0] rvfi_pc_wdata,
|
||||
output logic [31:0] rvfi_mem_addr,
|
||||
output logic [ 3:0] rvfi_mem_rmask,
|
||||
output logic [ 3:0] rvfi_mem_wmask,
|
||||
output logic [31:0] rvfi_mem_rdata,
|
||||
output logic [31:0] rvfi_mem_wdata,
|
||||
output logic rvfi_valid,
|
||||
output logic [63:0] rvfi_order,
|
||||
output logic [31:0] rvfi_insn,
|
||||
output logic rvfi_trap,
|
||||
output logic rvfi_halt,
|
||||
output logic rvfi_intr,
|
||||
output logic [ 1:0] rvfi_mode,
|
||||
output logic [ 1:0] rvfi_ixl,
|
||||
output logic [ 4:0] rvfi_rs1_addr,
|
||||
output logic [ 4:0] rvfi_rs2_addr,
|
||||
output logic [ 4:0] rvfi_rs3_addr,
|
||||
output logic [31:0] rvfi_rs1_rdata,
|
||||
output logic [31:0] rvfi_rs2_rdata,
|
||||
output logic [31:0] rvfi_rs3_rdata,
|
||||
output logic [ 4:0] rvfi_rd_addr,
|
||||
output logic [31:0] rvfi_rd_wdata,
|
||||
output logic [31:0] rvfi_pc_rdata,
|
||||
output logic [31:0] rvfi_pc_wdata,
|
||||
output logic [31:0] rvfi_mem_addr,
|
||||
output logic [ 3:0] rvfi_mem_rmask,
|
||||
output logic [ 3:0] rvfi_mem_wmask,
|
||||
output logic [31:0] rvfi_mem_rdata,
|
||||
output logic [31:0] rvfi_mem_wdata,
|
||||
`endif
|
||||
|
||||
// CPU Control Signals
|
||||
input logic fetch_enable_i,
|
||||
output logic alert_minor_o,
|
||||
output logic alert_major_o,
|
||||
output logic core_sleep_o,
|
||||
// CPU Control Signals
|
||||
input logic fetch_enable_i,
|
||||
output logic alert_minor_o,
|
||||
output logic alert_major_o,
|
||||
output logic core_sleep_o,
|
||||
|
||||
// DFT bypass controls
|
||||
input logic scan_rst_ni
|
||||
// DFT bypass controls
|
||||
input logic scan_rst_ni
|
||||
);
|
||||
|
||||
localparam bit Lockstep = SecureIbex;
|
||||
|
|
|
|||
|
|
@ -7,78 +7,78 @@
|
|||
*/
|
||||
|
||||
module ibex_top_tracing import ibex_pkg::*; #(
|
||||
parameter bit PMPEnable = 1'b0,
|
||||
parameter int unsigned PMPGranularity = 0,
|
||||
parameter int unsigned PMPNumRegions = 4,
|
||||
parameter int unsigned MHPMCounterNum = 0,
|
||||
parameter int unsigned MHPMCounterWidth = 40,
|
||||
parameter bit RV32E = 1'b0,
|
||||
parameter rv32m_e RV32M = RV32MFast,
|
||||
parameter rv32b_e RV32B = RV32BNone,
|
||||
parameter regfile_e RegFile = RegFileFF,
|
||||
parameter bit BranchTargetALU = 1'b0,
|
||||
parameter bit WritebackStage = 1'b0,
|
||||
parameter bit ICache = 1'b0,
|
||||
parameter bit ICacheECC = 1'b0,
|
||||
parameter bit BranchPredictor = 1'b0,
|
||||
parameter bit DbgTriggerEn = 1'b0,
|
||||
parameter int unsigned DbgHwBreakNum = 1,
|
||||
parameter bit SecureIbex = 1'b0,
|
||||
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
|
||||
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
|
||||
parameter int unsigned DmHaltAddr = 32'h1A110800,
|
||||
parameter int unsigned DmExceptionAddr = 32'h1A110808
|
||||
parameter bit PMPEnable = 1'b0,
|
||||
parameter int unsigned PMPGranularity = 0,
|
||||
parameter int unsigned PMPNumRegions = 4,
|
||||
parameter int unsigned MHPMCounterNum = 0,
|
||||
parameter int unsigned MHPMCounterWidth = 40,
|
||||
parameter bit RV32E = 1'b0,
|
||||
parameter rv32m_e RV32M = RV32MFast,
|
||||
parameter rv32b_e RV32B = RV32BNone,
|
||||
parameter regfile_e RegFile = RegFileFF,
|
||||
parameter bit BranchTargetALU = 1'b0,
|
||||
parameter bit WritebackStage = 1'b0,
|
||||
parameter bit ICache = 1'b0,
|
||||
parameter bit ICacheECC = 1'b0,
|
||||
parameter bit BranchPredictor = 1'b0,
|
||||
parameter bit DbgTriggerEn = 1'b0,
|
||||
parameter int unsigned DbgHwBreakNum = 1,
|
||||
parameter bit SecureIbex = 1'b0,
|
||||
parameter lfsr_seed_t RndCnstLfsrSeed = RndCnstLfsrSeedDefault,
|
||||
parameter lfsr_perm_t RndCnstLfsrPerm = RndCnstLfsrPermDefault,
|
||||
parameter int unsigned DmHaltAddr = 32'h1A110800,
|
||||
parameter int unsigned DmExceptionAddr = 32'h1A110808
|
||||
) (
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
// Clock and Reset
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
input logic test_en_i, // enable all clock gates for testing
|
||||
input logic scan_rst_ni,
|
||||
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
|
||||
input logic test_en_i, // enable all clock gates for testing
|
||||
input logic scan_rst_ni,
|
||||
input prim_ram_1p_pkg::ram_1p_cfg_t ram_cfg_i,
|
||||
|
||||
|
||||
input logic [31:0] hart_id_i,
|
||||
input logic [31:0] boot_addr_i,
|
||||
input logic [31:0] hart_id_i,
|
||||
input logic [31:0] boot_addr_i,
|
||||
|
||||
// Instruction memory interface
|
||||
output logic instr_req_o,
|
||||
input logic instr_gnt_i,
|
||||
input logic instr_rvalid_i,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic [6:0] instr_rdata_intg_i,
|
||||
input logic instr_err_i,
|
||||
// Instruction memory interface
|
||||
output logic instr_req_o,
|
||||
input logic instr_gnt_i,
|
||||
input logic instr_rvalid_i,
|
||||
output logic [31:0] instr_addr_o,
|
||||
input logic [31:0] instr_rdata_i,
|
||||
input logic [6:0] instr_rdata_intg_i,
|
||||
input logic instr_err_i,
|
||||
|
||||
// Data memory interface
|
||||
output logic data_req_o,
|
||||
input logic data_gnt_i,
|
||||
input logic data_rvalid_i,
|
||||
output logic data_we_o,
|
||||
output logic [3:0] data_be_o,
|
||||
output logic [31:0] data_addr_o,
|
||||
output logic [31:0] data_wdata_o,
|
||||
output logic [6:0] data_wdata_intg_o,
|
||||
input logic [31:0] data_rdata_i,
|
||||
input logic [6:0] data_rdata_intg_i,
|
||||
input logic data_err_i,
|
||||
// Data memory interface
|
||||
output logic data_req_o,
|
||||
input logic data_gnt_i,
|
||||
input logic data_rvalid_i,
|
||||
output logic data_we_o,
|
||||
output logic [3:0] data_be_o,
|
||||
output logic [31:0] data_addr_o,
|
||||
output logic [31:0] data_wdata_o,
|
||||
output logic [6:0] data_wdata_intg_o,
|
||||
input logic [31:0] data_rdata_i,
|
||||
input logic [6:0] data_rdata_intg_i,
|
||||
input logic data_err_i,
|
||||
|
||||
// Interrupt inputs
|
||||
input logic irq_software_i,
|
||||
input logic irq_timer_i,
|
||||
input logic irq_external_i,
|
||||
input logic [14:0] irq_fast_i,
|
||||
input logic irq_nm_i, // non-maskeable interrupt
|
||||
// Interrupt inputs
|
||||
input logic irq_software_i,
|
||||
input logic irq_timer_i,
|
||||
input logic irq_external_i,
|
||||
input logic [14:0] irq_fast_i,
|
||||
input logic irq_nm_i, // non-maskeable interrupt
|
||||
|
||||
// Debug Interface
|
||||
input logic debug_req_i,
|
||||
output crash_dump_t crash_dump_o,
|
||||
// Debug Interface
|
||||
input logic debug_req_i,
|
||||
output crash_dump_t crash_dump_o,
|
||||
|
||||
// CPU Control Signals
|
||||
input logic fetch_enable_i,
|
||||
output logic alert_minor_o,
|
||||
output logic alert_major_o,
|
||||
output logic core_sleep_o
|
||||
// CPU Control Signals
|
||||
input logic fetch_enable_i,
|
||||
output logic alert_minor_o,
|
||||
output logic alert_major_o,
|
||||
output logic core_sleep_o
|
||||
|
||||
);
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue