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[rtl] Fix zero value in FPGA RF

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We should use `WordZeroVal` instead of `0` for reads from register `x0` in the
FPGA register file.

This bug was discovered when enabling the `RegFileECC` parameter. When this is
enabled, the core performs ECC checks, expecting that `WordZeroVal` is returned
for `x0`. Else, we get a major alert.

Fixes lowRISC/opentitan#25146

Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
This commit is contained in:
Pascal Nasahl 2024-11-18 12:45:35 +01:00
parent f0f6bfd79a
commit a38e37342c
1 changed files with 4 additions and 4 deletions
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8
rtl/ibex_register_file_fpga.sv
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@ -147,14 +147,14 @@ module ibex_register_file_fpga #(
.out_o (mem_o_b)
);
assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem_o_a;
assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem_o_b;
assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem_o_a;
assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem_o_b;
end else begin : gen_no_rdata_mux_check
// async_read a
assign rdata_a_o = (raddr_a_i == '0) ? '0 : mem[raddr_a_i];
assign rdata_a_o = (raddr_a_i == '0) ? WordZeroVal : mem[raddr_a_i];
// async_read b
assign rdata_b_o = (raddr_b_i == '0) ? '0 : mem[raddr_b_i];
assign rdata_b_o = (raddr_b_i == '0) ? WordZeroVal : mem[raddr_b_i];
end
// we select