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Update doc to add data_err_i and LSU exceptions

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Pirmin Vogel 2019-05-21 11:08:55 +01:00 • committed by Philipp Wagner
parent 3cb868597f
commit a44e312e74
2 changed files with 40 additions and 27 deletions
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4
doc/exception_interrupts.rst
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@ -15,6 +15,8 @@ Ibex supports interrupts, exceptions on illegal instructions.
+------------+-----------------------------+
| **0x84** | Illegal Instruction |
+------------+-----------------------------+
| **0x8C** | LSU Error |
+------------+-----------------------------+
| **0x88** | ECALL Instruction Executed |
+------------+-----------------------------+
@ -32,7 +34,7 @@ Multiple interrupts requests are assumed to be handled by event/interrupt contro
Exceptions
----------
The illegal instruction exception and ecall instruction exceptions cannot be disabled and are always active.
The illegal instruction exception, LSU error exceptions and ecall instruction exceptions cannot be disabled and are always active.
Handling

63
doc/load_store_unit.rst
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@ -24,14 +24,19 @@ Signals that are used by the LSU:
| ``data_wdata_o[31:0]`` | output | Data to be written to memory, sent together |
| | | with ``data_req_o`` |
+-------------------------+-----------+-----------------------------------------------+
| ``data_rdata_i[31:0]`` | input | Data read from memory |
+-------------------------+-----------+-----------------------------------------------+
| ``data_rvalid_i`` | input | ``data_rdata_is`` holds valid data when |
| | | ``data_rvalid_i`` is high. This signal will |
| | | be high for exactly one cycle per request. |
+-------------------------+-----------+-----------------------------------------------+
| ``data_gnt_i`` | input | The other side accepted the request. |
| | | ``data_addr_o`` may change in the next cycle |
| | | Outputs may change in the next cycle. |
+-------------------------+-----------+-----------------------------------------------+
| ``data_rvalid_i`` | input | ``data_err_i`` and ``data_rdata_i`` hold |
| | | valid data when ``data_rvalid_i`` is high. |
| | | This signal will be high for exactly one |
| | | cycle per request. |
+-------------------------+-----------+-----------------------------------------------+
| ``data_err_i`` | input | Error response from the bus or the memory: |
| | | request cannot be handled. High in case of an |
| | | error. |
+-------------------------+-----------+-----------------------------------------------+
| ``data_rdata_i[31:0]`` | input | Data read from memory |
+-------------------------+-----------+-----------------------------------------------+
@ -47,7 +52,11 @@ Protocol
The protocol that is used by the LSU to communicate with a memory works as follows:
The LSU provides a valid address in ``data_addr_o`` and sets ``data_req_o`` high. The memory then answers with a ``data_gnt_i`` set high as soon as it is ready to serve the request. This may happen in the same cycle as the request was sent or any number of cycles later. After a grant was received, the address may be changed in the next cycle by the LSU. In addition, the ``data_wdata_o``, ``data_we_o`` and ``data_be_o`` signals may be changed as it is assumed that the memory has already processed and stored that information. After receiving a grant, the memory answers with a ``data_rvalid_i`` set high if ``data_rdata_i`` is valid. This may happen one or more cycles after the grant has been received. Note that ``data_rvalid_i`` must also be set when a write was performed, although the ``data_rdata_i`` has no meaning in this case.
1. The LSU provides a valid address in ``data_addr_o`` and sets ``data_req_o`` high. In the case of a store, the LSU also sets ``data_we_o`` high and configures ``data_be_o`` and ``data_wdata_o``. The memory then answers with a ``data_gnt_i`` set high as soon as it is ready to serve the request. This may happen in the same cycle as the request was sent or any number of cycles later.
2. After receiving a grant, the address may be changed in the next cycle by the LSU. In addition, the ``data_wdata_o``, ``data_we_o`` and ``data_be_o`` signals may be changed as it is assumed that the memory has already processed and stored that information.
3. The memory answers with a ``data_rvalid_i`` set high for exactly one cycle to signal the response from the bus or the memory using ``data_err_i`` and ``data_rdata_i`` (during the very same cycle). This may happen one or more cycles after the grant has been received. If ``data_err_i`` is low, the request could successfully be handled at the destination and in the case of a load, ``data_rdata_i`` contains valid data. If ``data_err_i`` is high, an error occured in the memory system and the core will raise an exception.
:numref:`timing1`, :numref:`timing2` and :numref:`timing3` show example-timing diagrams of the protocol.
@ -58,19 +67,20 @@ The LSU provides a valid address in ``data_addr_o`` and sets ``data_req_o`` high
{"signal":
[
{"name": "clk", "wave": "p......"},
{"name": "data_addr_o", "wave": "x=.xxxx", "data": ["Address"]},
{"name": "data_wdata_o", "wave": "x=.xxxx", "data": ["WData"]},
{"name": "data_req_o", "wave": "01.0..."},
{"name": "data_addr_o", "wave": "x=.xxxx", "data": ["Address"]},
{"name": "data_we_o", "wave": "x=.xxxx", "data": ["WE"]},
{"name": "data_be_o", "wave": "x=.xxxx", "data": ["BE"]},
{"name": "data_wdata_o", "wave": "x=.xxxx", "data": ["WData"]},
{"name": "data_gnt_i", "wave": "0.10..."},
{"name": "data_rvalid_i", "wave": "0..10.."},
{"name": "data_wdata_o", "wave": "xxx=xxx", "data": ["RData"]},
{"name": "data_we_o", "wave": "x=.xxxx", "data": ["WE"]},
{"name": "data_be_o", "wave": "x=.xxxx", "data": ["BE"]}
{"name": "data_err_i", "wave": "xxx=xxx", "data": ["Err"]},
{"name": "data_rdata_i", "wave": "xxx=xxx", "data": ["RData"]}
],
"config": { "hscale": 2 }
}
.. wavedrom::
:name: timing2
:caption: Back-to-back Memory Transaction
@ -78,18 +88,18 @@ The LSU provides a valid address in ``data_addr_o`` and sets ``data_req_o`` high
{"signal":
[
{"name": "clk", "wave": "p......"},
{"name": "data_addr_o", "wave": "x==xxxx", "data": ["Addr1", "Addr2"]},
{"name": "data_wdata_o", "wave": "x==xxxx", "data": ["WData1", "Wdata2"]},
{"name": "data_req_o", "wave": "01.0..."},
{"name": "data_gnt_i", "wave": "01.0..."},
{"name": "data_rvalid_i", "wave": "0.1.0.."},
{"name": "data_wdata_o", "wave": "xx==xxx", "data": ["RData1", "RData2"]},
{"name": "data_addr_o", "wave": "x==xxxx", "data": ["Addr1", "Addr2"]},
{"name": "data_we_o", "wave": "x==xxxx", "data": ["WE1", "WE2"]},
{"name": "data_be_o", "wave": "x==xxxx", "data": ["BE1", "BE2"]}
{"name": "data_be_o", "wave": "x==xxxx", "data": ["BE1", "BE2"]},
{"name": "data_wdata_o", "wave": "x==xxxx", "data": ["WData1", "Wdata2"]},
{"name": "data_gnt_i", "wave": "01.0..."},
{"name": "data_rvalid_i", "wave": "0.1.0.."},
{"name": "data_err_i", "wave": "xx==xxx", "data": ["Err1", "Err2"]},
{"name": "data_rdata_i", "wave": "xx==xxx", "data": ["RData1", "RData2"]}
],
"config": { "hscale": 2 }
}
.. wavedrom::
:name: timing3
@ -98,14 +108,15 @@ The LSU provides a valid address in ``data_addr_o`` and sets ``data_req_o`` high
{"signal":
[
{"name": "clk", "wave": "p......"},
{"name": "data_addr_o", "wave": "x=..xxx", "data": ["Address"]},
{"name": "data_wdata_o", "wave": "x=..xxx", "data": ["WData"]},
{"name": "data_req_o", "wave": "01..0.."},
{"name": "data_addr_o", "wave": "x=..xxx", "data": ["Address"]},
{"name": "data_we_o", "wave": "x=..xxx", "data": ["WE"]},
{"name": "data_be_o", "wave": "x=..xxx", "data": ["BE"]},
{"name": "data_wdata_o", "wave": "x=..xxx", "data": ["WData"]},
{"name": "data_gnt_i", "wave": "0..10.."},
{"name": "data_rvalid_i", "wave": "0....10"},
{"name": "data_wdata_o", "wave": "xxxxx=x", "data": ["RData"]},
{"name": "data_we_o", "wave": "x=..xxx", "data": ["WE"]},
{"name": "data_be_o", "wave": "x=..xxx", "data": ["BE"]}
{"name": "data_err_i", "wave": "xxxxx=x", "data": ["Err"]},
{"name": "data_rdata_i", "wave": "xxxxx=x", "data": ["RData"]}
],
"config": { "hscale": 2 }
}