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fix misalignement memory access

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This commit is contained in:
Pasquale Davide Schiavone 2017-07-07 17:17:28 +02:00
parent ad0b3383c0
commit a6d33442be
1 changed files with 2 additions and 1 deletions
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3
zeroriscy_load_store_unit.sv
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@ -391,11 +391,12 @@ module zeroriscy_load_store_unit
increase_address = 1'b0;
//tell the controller to update the address
data_misaligned_o = 1'b1;
data_req_o = 1'b1; //maybe better if controller handles this
data_req_o = 1'b0;
lsu_update_addr_o = data_gnt_i;
if(data_rvalid_i) begin
//if first part rvalid is received
data_req_o = 1'b1;
if(data_gnt_i) begin
//second grant is received
NS = WAIT_RVALID;