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fix for verilator by Olivier Montfort

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This commit is contained in:
Pasquale Davide Schiavone 2017-10-04 17:09:23 +02:00
parent 170571c496
commit aa41918a60
2 changed files with 14 additions and 12 deletions
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20
zeroriscy_fetch_fifo.sv
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@ -50,9 +50,9 @@ module zeroriscy_fetch_fifo
localparam DEPTH = 3; // must be 3 or greater
// index 0 is used for output
logic [0:DEPTH-1] [31:0] addr_n, addr_int, addr_Q;
logic [0:DEPTH-1] [31:0] rdata_n, rdata_int, rdata_Q;
logic [0:DEPTH-1] valid_n, valid_int, valid_Q;
logic [DEPTH-1:0] [31:0] addr_n, addr_int, addr_Q;
logic [DEPTH-1:0] [31:0] rdata_n, rdata_int, rdata_Q;
logic [DEPTH-1:0] valid_n, valid_int, valid_Q;
logic [31:0] addr_next;
logic [31:0] rdata, rdata_unaligned;
@ -137,11 +137,11 @@ module zeroriscy_fetch_fifo
always_comb
begin
int j;
addr_int = addr_Q;
rdata_int = rdata_Q;
valid_int = valid_Q;
if (in_valid_i) begin
for(j = 0; j < DEPTH; j++) begin
@ -176,18 +176,18 @@ module zeroriscy_fetch_fifo
addr_n[0] = {addr_next[31:2], 2'b10};
end
rdata_n = {rdata_int[1:DEPTH-1], 32'b0};
valid_n = {valid_int[1:DEPTH-1], 1'b0};
rdata_n = {rdata_int[DEPTH-1:1], 32'b0};
valid_n = {valid_int[DEPTH-1:1], 1'b0};
end else begin
if (aligned_is_compressed) begin
// just increase address, do not move to next entry in FIFO
addr_n[0] = {addr_int[0][31:2], 2'b10};
end else begin
// move to next entry in FIFO
addr_n[0] = {addr_next[31:2], 2'b00};
rdata_n = {rdata_int[1:DEPTH-1], 32'b0};
valid_n = {valid_int[1:DEPTH-1], 1'b0};
rdata_n = {rdata_int[DEPTH-1:1], 32'b0};
valid_n = {valid_int[DEPTH-1:1], 1'b0};
end
end
end

6
zeroriscy_register_file_ff.sv
View file

@ -58,6 +58,7 @@ module zeroriscy_register_file
localparam NUM_WORDS = 2**ADDR_WIDTH;
logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] rf_reg;
logic [NUM_WORDS-1:0][DATA_WIDTH-1:0] rf_reg_tmp;
logic [NUM_WORDS-1:0] we_a_dec;
always_comb
@ -81,10 +82,10 @@ module zeroriscy_register_file
always_ff @(posedge clk, negedge rst_n)
begin : register_write_behavioral
if (rst_n==1'b0) begin
rf_reg[i] <= 'b0;
rf_reg_tmp[i] <= 'b0;
end else begin
if (we_a_dec[i])
rf_reg[i] <= wdata_a_i;
rf_reg_tmp[i] <= wdata_a_i;
end
end
@ -92,6 +93,7 @@ module zeroriscy_register_file
// R0 is nil
assign rf_reg[0] = '0;
assign rf_reg[NUM_WORDS-1:1] = rf_reg_tmp[NUM_WORDS-1:1];
endgenerate