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Simplify default assignments to enum types
This commit simplifies the assignment of literals to enum types in default cases by: - defining or using existing enum values for all-zero values, - feeding a single `1'bX` into the type cast instead of exact width (the tools are fine with that).
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036f963990
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8 changed files with 16 additions and 14 deletions
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@ -163,10 +163,10 @@ module ibex_controller (
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csr_save_cause_o = 1'b0;
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exc_cause_o = exc_cause_e'({$bits(exc_cause_e){1'b0}});
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exc_cause_o = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00
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exc_pc_mux_o = EXC_PC_IRQ;
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csr_cause_o = exc_cause_e'({$bits(exc_cause_e){1'b0}});
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csr_cause_o = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00
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pc_mux_o = PC_BOOT;
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pc_set_o = 1'b0;
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@ -513,7 +513,7 @@ module ibex_controller (
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default: begin
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instr_req_o = 1'b0;
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ctrl_fsm_ns = ctrl_fsm_e'({$bits(ctrl_fsm_e){1'bX}});
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ctrl_fsm_ns = ctrl_fsm_e'(1'bX);
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end
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endcase
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end
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@ -239,7 +239,7 @@ module ibex_cs_registers #(
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mstatus_n = '{
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mie: csr_wdata_int[`MSTATUS_MIE_BITS],
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mpie: csr_wdata_int[`MSTATUS_MPIE_BITS],
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mpp: priv_lvl_e'(PRIV_LVL_M)
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mpp: PRIV_LVL_M
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};
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end
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// mepc: exception program counter
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@ -371,8 +371,8 @@ module ibex_cs_registers #(
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depc_q <= '0;
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dcsr_q <= '{
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xdebugver: x_debug_ver_e'({$bits(x_debug_ver_e){1'b0}}),
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cause: dbg_cause_e'({$bits(dbg_cause_e){1'b0}}),
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xdebugver: XDEBUGVER_NO, // 4'h0
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cause: DBG_CAUSE_NONE, // 3'h0
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prv: PRIV_LVL_M,
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default: '0
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};
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@ -112,8 +112,8 @@ typedef enum logic[1:0] {
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// Constants for the dcsr.xdebugver fields
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typedef enum logic[3:0] {
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XDEBUGVER_NO = 4'd0, // no external debug support
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XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec
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XDEBUGVER_NO = 4'd0, // no external debug support
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XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec
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XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec
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} x_debug_ver_e;
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@ -185,6 +185,7 @@ typedef enum logic [2:0] {
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// Exception cause
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typedef enum logic [5:0] {
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EXC_CAUSE_INSN_ADDR_MISA = 6'h00,
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EXC_CAUSE_ILLEGAL_INSN = 6'h02,
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EXC_CAUSE_BREAKPOINT = 6'h03,
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EXC_CAUSE_LOAD_ACCESS_FAULT = 6'h05,
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@ -209,6 +210,7 @@ typedef enum logic [7:0] {
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// Debug cause
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typedef enum logic [2:0] {
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DBG_CAUSE_NONE = 3'h0,
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DBG_CAUSE_EBREAK = 3'h1,
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DBG_CAUSE_TRIGGER = 3'h2,
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DBG_CAUSE_HALTREQ = 3'h3,
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@ -87,7 +87,7 @@ module ibex_int_controller (
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end
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default: begin
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exc_ctrl_ns = exc_ctrl_e'({$bits(exc_ctrl_e){1'bX}});
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exc_ctrl_ns = exc_ctrl_e'(1'bX);
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end
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endcase
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end
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@ -423,7 +423,7 @@ module ibex_load_store_unit (
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end //~ WAIT_RVALID
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default: begin
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ls_fsm_ns = ls_fsm_e'({$bits(ls_fsm_e){1'bX}});
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ls_fsm_ns = ls_fsm_e'(1'bX);
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end
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endcase
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end
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@ -247,7 +247,7 @@ module ibex_multdiv_fast (
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end
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default: begin
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divcurr_state_n = div_fsm_e'({$bits(div_fsm_e){1'bX}});
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divcurr_state_n = div_fsm_e'(1'bX);
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end
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endcase // divcurr_state_q
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end
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@ -327,7 +327,7 @@ module ibex_multdiv_fast (
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mult_is_ready = 1'b1;
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end
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default: begin
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mult_state_n = mult_fsm_e'({$bits(mult_fsm_e){1'bX}});
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mult_state_n = mult_fsm_e'(1'bX);
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end
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endcase // mult_state_q
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end
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@ -284,7 +284,7 @@ module ibex_multdiv_slow (
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end
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default: begin
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curr_state_d = div_fsm_e'({$bits(div_fsm_e){1'bX}});
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curr_state_d = div_fsm_e'(1'bX);
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end
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endcase // curr_state_q
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end
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@ -200,7 +200,7 @@ module ibex_prefetch_buffer (
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end
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default: begin
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NS = prefetch_fsm_e'({$bits(prefetch_fsm_e){1'bX}});
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NS = prefetch_fsm_e'(1'bX);
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end
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endcase
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end
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