Simplify default assignments to enum types

This commit simplifies the assignment of literals to enum types in
default cases by:
- defining or using existing enum values for all-zero values,
- feeding a single `1'bX` into the type cast instead of exact width
  (the tools are fine with that).
This commit is contained in:
Pirmin Vogel 2019-05-24 14:29:00 +01:00
parent 036f963990
commit ab4c8699fb
8 changed files with 16 additions and 14 deletions

View file

@ -163,10 +163,10 @@ module ibex_controller (
csr_save_cause_o = 1'b0;
exc_cause_o = exc_cause_e'({$bits(exc_cause_e){1'b0}});
exc_cause_o = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00
exc_pc_mux_o = EXC_PC_IRQ;
csr_cause_o = exc_cause_e'({$bits(exc_cause_e){1'b0}});
csr_cause_o = EXC_CAUSE_INSN_ADDR_MISA; // = 6'h00
pc_mux_o = PC_BOOT;
pc_set_o = 1'b0;
@ -513,7 +513,7 @@ module ibex_controller (
default: begin
instr_req_o = 1'b0;
ctrl_fsm_ns = ctrl_fsm_e'({$bits(ctrl_fsm_e){1'bX}});
ctrl_fsm_ns = ctrl_fsm_e'(1'bX);
end
endcase
end

View file

@ -239,7 +239,7 @@ module ibex_cs_registers #(
mstatus_n = '{
mie: csr_wdata_int[`MSTATUS_MIE_BITS],
mpie: csr_wdata_int[`MSTATUS_MPIE_BITS],
mpp: priv_lvl_e'(PRIV_LVL_M)
mpp: PRIV_LVL_M
};
end
// mepc: exception program counter
@ -371,8 +371,8 @@ module ibex_cs_registers #(
depc_q <= '0;
dcsr_q <= '{
xdebugver: x_debug_ver_e'({$bits(x_debug_ver_e){1'b0}}),
cause: dbg_cause_e'({$bits(dbg_cause_e){1'b0}}),
xdebugver: XDEBUGVER_NO, // 4'h0
cause: DBG_CAUSE_NONE, // 3'h0
prv: PRIV_LVL_M,
default: '0
};

View file

@ -112,8 +112,8 @@ typedef enum logic[1:0] {
// Constants for the dcsr.xdebugver fields
typedef enum logic[3:0] {
XDEBUGVER_NO = 4'd0, // no external debug support
XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec
XDEBUGVER_NO = 4'd0, // no external debug support
XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec
XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec
} x_debug_ver_e;
@ -185,6 +185,7 @@ typedef enum logic [2:0] {
// Exception cause
typedef enum logic [5:0] {
EXC_CAUSE_INSN_ADDR_MISA = 6'h00,
EXC_CAUSE_ILLEGAL_INSN = 6'h02,
EXC_CAUSE_BREAKPOINT = 6'h03,
EXC_CAUSE_LOAD_ACCESS_FAULT = 6'h05,
@ -209,6 +210,7 @@ typedef enum logic [7:0] {
// Debug cause
typedef enum logic [2:0] {
DBG_CAUSE_NONE = 3'h0,
DBG_CAUSE_EBREAK = 3'h1,
DBG_CAUSE_TRIGGER = 3'h2,
DBG_CAUSE_HALTREQ = 3'h3,

View file

@ -87,7 +87,7 @@ module ibex_int_controller (
end
default: begin
exc_ctrl_ns = exc_ctrl_e'({$bits(exc_ctrl_e){1'bX}});
exc_ctrl_ns = exc_ctrl_e'(1'bX);
end
endcase
end

View file

@ -423,7 +423,7 @@ module ibex_load_store_unit (
end //~ WAIT_RVALID
default: begin
ls_fsm_ns = ls_fsm_e'({$bits(ls_fsm_e){1'bX}});
ls_fsm_ns = ls_fsm_e'(1'bX);
end
endcase
end

View file

@ -247,7 +247,7 @@ module ibex_multdiv_fast (
end
default: begin
divcurr_state_n = div_fsm_e'({$bits(div_fsm_e){1'bX}});
divcurr_state_n = div_fsm_e'(1'bX);
end
endcase // divcurr_state_q
end
@ -327,7 +327,7 @@ module ibex_multdiv_fast (
mult_is_ready = 1'b1;
end
default: begin
mult_state_n = mult_fsm_e'({$bits(mult_fsm_e){1'bX}});
mult_state_n = mult_fsm_e'(1'bX);
end
endcase // mult_state_q
end

View file

@ -284,7 +284,7 @@ module ibex_multdiv_slow (
end
default: begin
curr_state_d = div_fsm_e'({$bits(div_fsm_e){1'bX}});
curr_state_d = div_fsm_e'(1'bX);
end
endcase // curr_state_q
end

View file

@ -200,7 +200,7 @@ module ibex_prefetch_buffer (
end
default: begin
NS = prefetch_fsm_e'({$bits(prefetch_fsm_e){1'bX}});
NS = prefetch_fsm_e'(1'bX);
end
endcase
end