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[dv] fix timing issue in single_step test (#749)

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Signed-off-by: Udi <udij@google.com>
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udinator 2020-03-31 11:59:01 -07:00 • committed by GitHub
parent 7dae33abc2
commit add91d544d
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1 changed files with 1 additions and 1 deletions
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dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
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@ -739,6 +739,7 @@ class core_ibex_debug_single_step_test extends core_ibex_directed_test;
bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] counter = 0;
bit [ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] next_counter = 0;
forever begin
clk_vif.wait_clks(2000);
vseq.start_debug_single_seq();
check_next_core_status(IN_DEBUG_MODE,
"Core did not enter debug mode after debug stimulus", 1000);
@ -779,7 +780,6 @@ class core_ibex_debug_single_step_test extends core_ibex_directed_test;
wait_ret("dret", 5000);
if (counter === 0) break;
end
clk_vif.wait_clks(2000);
end
endtask