github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-20 11:57:12 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

updates

Browse source
This commit is contained in:
Pasquale Davide Schiavone 2017-03-02 12:00:26 +01:00
parent 480a02a417
commit af5903f76f
4 changed files with 9 additions and 42 deletions
Download patch file Download diff file Expand all files Collapse all files

35
id_stage.sv
View file

@ -88,7 +88,6 @@ module zeroriscy_id_stage
output logic [ALU_OP_WIDTH-1:0] alu_operator_ex_o,
output logic [31:0] alu_operand_a_ex_o,
output logic [31:0] alu_operand_b_ex_o,
output logic [31:0] alu_operand_c_ex_o, // Still needed if 2r1w reg file used
// CSR ID
output logic csr_access_ex_o,
@ -101,6 +100,7 @@ module zeroriscy_id_stage
output logic data_sign_ext_ex_o,
output logic [1:0] data_reg_offset_ex_o,
output logic data_load_event_ex_o,
output logic [31:0] data_wdata_ex_o,
input logic data_misaligned_i,
input logic [31:0] misaligned_addr_i,
@ -240,7 +240,6 @@ module zeroriscy_id_stage
logic [31:0] alu_operand_a;
logic [31:0] alu_operand_b;
logic [31:0] alu_operand_c; // Still needed if 2r1w reg file used
assign instr = instr_rdata_i;
@ -362,28 +361,6 @@ module zeroriscy_id_stage
assign alu_operand_b = operand_b;
assign operand_b_fw_id = operand_b;
//////////////////////////////////////////////////////
// ___ _ ____ //
// / _ \ _ __ ___ _ __ __ _ _ __ __| | / ___| //
// | | | | '_ \ / _ \ '__/ _` | '_ \ / _` | | | //
// | |_| | |_) | __/ | | (_| | | | | (_| | | |___ //
// \___/| .__/ \___|_| \__,_|_| |_|\__,_| \____| //
// |_| //
//////////////////////////////////////////////////////
// ALU OP C Mux, jump or store. TODO: Change it
/*
always_comb
begin : alu_operand_c_mux
case (alu_op_c_mux_sel)
OP_C_REGB_OR_FWD: alu_operand_c = regfile_data_rb_id;
OP_C_RA: alu_operand_c = pc_if_i; // this is the return address
default: alu_operand_c = regfile_data_rb_id;
endcase // case (alu_op_c_mux_sel)
end
*/
assign alu_operand_c = regfile_data_rb_id;
/////////////////////////////////////////////////////////
// ____ _____ ____ ___ ____ _____ _____ ____ ____ //
// | _ \| ____/ ___|_ _/ ___|_ _| ____| _ \/ ___| //
@ -640,20 +617,18 @@ module zeroriscy_id_stage
assign data_we_ex_o = data_we_id;
assign data_type_ex_o = data_type_id;
assign data_sign_ext_ex_o = data_sign_ext_id;
assign data_wdata_ex_o = regfile_data_rb_id;
assign data_req_ex_o = data_req_id;
assign data_reg_offset_ex_o = data_reg_offset_id;
assign data_load_event_ex_o = ((data_req_id & (~halt_id)) ? data_load_event_id : 1'b0);
assign alu_operator_ex_o = alu_operator;
assign alu_operand_a_ex_o = alu_operand_a;
assign alu_operand_b_ex_o = alu_operand_b;
assign alu_operand_c_ex_o = alu_operand_c;
assign csr_access_ex_o = csr_access;
assign csr_op_ex_o = id_ready_o ? csr_op : CSR_OP_NONE;
assign data_req_ex_o = data_req_id;
assign data_reg_offset_ex_o = data_reg_offset_id;
assign data_load_event_ex_o = ((data_req_id & (~halt_id)) ? data_load_event_id : 1'b0);
assign branch_in_ex_o = branch_in_id;
enum logic { IDLE, WAIT_MULTICYCLE } id_wb_fsm_cs, id_wb_fsm_ns;

1
if_stage.sv
View file

@ -118,7 +118,6 @@ module zeroriscy_if_stage #(
unique case (pc_mux_i)
PC_BOOT: fetch_addr_n = {boot_addr_i[31:8], EXC_OFF_RST};
PC_JUMP: fetch_addr_n = jump_target_ex_i;
PC_BRANCH: fetch_addr_n = jump_target_ex_i;
PC_EXCEPTION: fetch_addr_n = exc_pc; // set PC to exception handler
PC_ERET: fetch_addr_n = exception_pc_reg_i; // PC is restored when returning from IRQ/exception
PC_DBG_NPC: fetch_addr_n = dbg_jump_addr_i; // PC is taken from debug unit

1
include/zeroriscy_defines.sv
View file

@ -288,7 +288,6 @@ parameter JT_COND = 2'b11;
// PC mux selector defines
parameter PC_BOOT = 3'b000;
parameter PC_JUMP = 3'b010;
parameter PC_BRANCH = 3'b011;
parameter PC_EXCEPTION = 3'b100;
parameter PC_ERET = 3'b101;
parameter PC_DBG_NPC = 3'b111;

14
zeroriscy_core.sv
View file

@ -131,7 +131,6 @@ module zeroriscy_core
logic [ALU_OP_WIDTH-1:0] alu_operator_ex;
logic [31:0] alu_operand_a_ex;
logic [31:0] alu_operand_b_ex;
logic [31:0] alu_operand_c_ex;
logic [31:0] alu_adder_result_ex; // Used to forward computed address to LSU
logic [31:0] regfile_wdata_ex;
@ -153,7 +152,7 @@ module zeroriscy_core
logic data_sign_ext_ex;
logic [1:0] data_reg_offset_ex;
logic data_req_ex;
logic [31:0] data_pc_ex;
logic [31:0] data_wdata_ex;
logic data_load_event_ex;
logic data_misaligned_ex;
logic [31:0] regfile_wdata_lsu;
@ -381,9 +380,6 @@ module zeroriscy_core
.alu_operator_ex_o ( alu_operator_ex ),
.alu_operand_a_ex_o ( alu_operand_a_ex ),
.alu_operand_b_ex_o ( alu_operand_b_ex ),
//used in LSU for store instructions
//TODO: change name
.alu_operand_c_ex_o ( alu_operand_c_ex ),
// CSR ID/EX
.csr_access_ex_o ( csr_access_ex ),
@ -396,6 +392,7 @@ module zeroriscy_core
.data_sign_ext_ex_o ( data_sign_ext_ex ), // to load store unit
.data_reg_offset_ex_o ( data_reg_offset_ex ), // to load store unit
.data_load_event_ex_o ( data_load_event_ex ), // to load store unit
.data_wdata_ex_o ( data_wdata_ex ), // to load store unit
.data_misaligned_i ( data_misaligned ),
.misaligned_addr_i ( misaligned_addr ),
@ -493,7 +490,7 @@ module zeroriscy_core
// signal from ex stage
.data_we_ex_i ( data_we_ex ),
.data_type_ex_i ( data_type_ex ),
.data_wdata_ex_i ( alu_operand_c_ex ),
.data_wdata_ex_i ( data_wdata_ex ),
.data_reg_offset_ex_i ( data_reg_offset_ex ),
.data_sign_ext_ex_i ( data_sign_ext_ex ), // sign extension
@ -650,9 +647,6 @@ module zeroriscy_core
.sleeping_i ( sleeping ),
.branch_in_ex_i ( branch_in_ex ),
.branch_taken_i ( branch_decision ),
.jump_addr_o ( dbg_jump_addr ), // PC from debug unit
.jump_req_o ( dbg_jump_req ) // set PC to new value
);
@ -677,7 +671,7 @@ module zeroriscy_core
.rs1_value ( id_stage_i.operand_a_fw_id ),
.rs2_value ( id_stage_i.operand_b_fw_id ),
.rs3_value ( id_stage_i.alu_operand_c ),
.rs3_value ( data_wdata_ex ),
.rs2_value_vec ( id_stage_i.alu_operand_b ),
.ex_valid ( ),