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https://github.com/lowRISC/ibex.git
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[RTL] Keep instr in ID valid for FLUSH state
When an instruction that caused an exception occurred the controller would clear the instr_valid bit but rely on the instruction bits staying in the ID register so it could still use them in the FLUSH state to decide what to do. This reworks the control logic slightly so instr_valid remains asserted when the controller goes into the FLUSH state so relevant signals can be qualified with the instr_valid bit. There were no known functional issues caused by the previous behaviour however this gives a more robust approach.
This commit is contained in:
Greg Chadwick
parent
252874d32d
commit
b1155740c2
2 changed files with 47 additions and 25 deletions
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@ -104,7 +104,7 @@ module ibex_controller (
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logic stall;
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logic halt_if;
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logic halt_id;
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logic flush_id;
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logic illegal_dret;
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logic illegal_insn;
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logic exc_req;
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@ -116,6 +116,14 @@ module ibex_controller (
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logic [3:0] mfip_id;
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logic unused_csr_mtip;
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logic ecall_insn;
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logic mret_insn;
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logic dret_insn;
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logic wfi_insn;
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logic ebrk_insn;
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logic csr_pipe_flush;
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logic instr_fetch_err;
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`ifndef SYNTHESIS
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// synopsys translate_off
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// make sure we are called later so that we do not generate messages for
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@ -137,19 +145,28 @@ module ibex_controller (
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assign load_err_d = load_err_i;
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assign store_err_d = store_err_i;
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// Decoder doesn't take instr_valid into account, factor it in here.
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assign ecall_insn = ecall_insn_i & instr_valid_i;
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assign mret_insn = mret_insn_i & instr_valid_i;
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assign dret_insn = dret_insn_i & instr_valid_i;
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assign wfi_insn = wfi_insn_i & instr_valid_i;
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assign ebrk_insn = ebrk_insn_i & instr_valid_i;
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assign csr_pipe_flush = csr_pipe_flush_i & instr_valid_i;
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assign instr_fetch_err = instr_fetch_err_i & instr_valid_i;
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// "Executing DRET outside of Debug Mode causes an illegal instruction exception."
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// [Debug Spec v0.13.2, p.41]
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assign illegal_dret = dret_insn_i & ~debug_mode_q;
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assign illegal_dret = dret_insn & ~debug_mode_q;
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assign illegal_insn = illegal_insn_i | illegal_dret;
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// exception requests
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assign exc_req = ecall_insn_i | ebrk_insn_i | illegal_insn | instr_fetch_err_i;
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assign exc_req = ecall_insn | ebrk_insn | illegal_insn | instr_fetch_err;
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// LSU exception requests
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assign exc_req_lsu = store_err_i | load_err_i;
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// special requests: special instructions, pipeline flushes, exceptions...
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assign special_req = mret_insn_i | dret_insn_i | wfi_insn_i | csr_pipe_flush_i |
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assign special_req = mret_insn | dret_insn | wfi_insn | csr_pipe_flush |
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exc_req | exc_req_lsu;
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////////////////
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@ -210,7 +227,7 @@ module ibex_controller (
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first_fetch_o = 1'b0;
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halt_if = 1'b0;
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halt_id = 1'b0;
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flush_id = 1'b0;
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debug_csr_save_o = 1'b0;
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debug_cause_o = DBG_CAUSE_EBREAK;
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@ -244,7 +261,7 @@ module ibex_controller (
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ctrl_busy_o = 1'b0;
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instr_req_o = 1'b0;
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halt_if = 1'b1;
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halt_id = 1'b1;
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flush_id = 1'b1;
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ctrl_fsm_ns = SLEEP;
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end
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@ -254,7 +271,7 @@ module ibex_controller (
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ctrl_busy_o = 1'b0;
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instr_req_o = 1'b0;
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halt_if = 1'b1;
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halt_id = 1'b1;
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flush_id = 1'b1;
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// normal execution flow
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// in debug mode or single step mode we leave immediately (wfi=nop)
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@ -276,14 +293,14 @@ module ibex_controller (
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// going to sleep.
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ctrl_fsm_ns = IRQ_TAKEN;
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halt_if = 1'b1;
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halt_id = 1'b1;
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flush_id = 1'b1;
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end
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// enter debug mode
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if (enter_debug_mode) begin
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ctrl_fsm_ns = DBG_TAKEN_IF;
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halt_if = 1'b1;
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halt_id = 1'b1;
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flush_id = 1'b1;
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end
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end
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@ -298,9 +315,11 @@ module ibex_controller (
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// get ready for special instructions, exceptions, pipeline flushes
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if (special_req) begin
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ctrl_fsm_ns = FLUSH;
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halt_if = 1'b1;
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halt_id = 1'b1;
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// Halt IF but don't flush ID. This leaves a valid instruction in
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// ID so controller can determine appropriate action in the
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// FLUSH state.
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ctrl_fsm_ns = FLUSH;
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halt_if = 1'b1;
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// set PC in IF stage to branch or jump target
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end else if (branch_set_i || jump_set_i) begin
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pc_mux_o = PC_JUMP;
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@ -334,13 +353,13 @@ module ibex_controller (
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// enter debug mode
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ctrl_fsm_ns = DBG_TAKEN_IF;
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halt_if = 1'b1;
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halt_id = 1'b1;
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flush_id = 1'b1;
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end else if (handle_irq) begin
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// handle interrupt (not in debug mode)
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ctrl_fsm_ns = IRQ_TAKEN;
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halt_if = 1'b1;
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halt_id = 1'b1;
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flush_id = 1'b1;
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end
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end
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@ -410,7 +429,7 @@ module ibex_controller (
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//
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// for 1. do not update dcsr and dpc, for 2. do so [Debug Spec v0.13.2, p.39]
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// jump to debug exception handler in debug memory
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if (ebrk_insn_i) begin
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if (ebrk_insn) begin
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pc_mux_o = PC_EXC;
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pc_set_o = 1'b1;
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exc_pc_mux_o = EXC_PC_DBD;
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@ -437,7 +456,7 @@ module ibex_controller (
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FLUSH: begin
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// flush the pipeline
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halt_if = 1'b1;
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halt_id = 1'b1;
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flush_id = 1'b1;
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ctrl_fsm_ns = DECODE;
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// exceptions: set exception PC, save PC and exception cause
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@ -450,7 +469,7 @@ module ibex_controller (
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csr_save_cause_o = 1'b1;
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// set exception registers, priorities according to Table 3.7 of Privileged Spec v1.11
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if (instr_fetch_err_i) begin
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if (instr_fetch_err) begin
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exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT;
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csr_mtval_o = pc_id_i;
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@ -458,10 +477,10 @@ module ibex_controller (
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exc_cause_o = EXC_CAUSE_ILLEGAL_INSN;
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csr_mtval_o = instr_is_compressed_i ? {16'b0, instr_compressed_i} : instr_i;
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end else if (ecall_insn_i) begin
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end else if (ecall_insn) begin
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exc_cause_o = EXC_CAUSE_ECALL_MMODE;
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end else if (ebrk_insn_i) begin
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end else if (ebrk_insn) begin
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if (debug_mode_q) begin
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/*
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* EBREAK in debug mode re-enters debug mode
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@ -508,20 +527,20 @@ module ibex_controller (
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end else begin
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// special instructions and pipeline flushes
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if (mret_insn_i) begin
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if (mret_insn) begin
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pc_mux_o = PC_ERET;
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pc_set_o = 1'b1;
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csr_restore_mret_id_o = 1'b1;
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if (nmi_mode_q) begin
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nmi_mode_d = 1'b0; // exit NMI mode
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end
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end else if (dret_insn_i) begin
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end else if (dret_insn) begin
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pc_mux_o = PC_DRET;
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pc_set_o = 1'b1;
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debug_mode_d = 1'b0;
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end else if (wfi_insn_i) begin
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end else if (wfi_insn) begin
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ctrl_fsm_ns = WAIT_SLEEP;
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end else if (csr_pipe_flush_i && handle_irq) begin
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end else if (csr_pipe_flush && handle_irq) begin
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// start handling IRQs when doing CSR-related pipeline flushes
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ctrl_fsm_ns = IRQ_TAKEN;
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end
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@ -559,7 +578,10 @@ module ibex_controller (
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// kill instr in IF-ID pipeline reg that are done, or if a
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// multicycle instr causes an exception for example
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assign instr_valid_clear_o = ~stall | halt_id;
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// halt_if is another kind of stall, where the instr_valid bit must remain
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// set (unless flush_id is set also). It cannot be factored directly into
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// stall as this causes a combinational loop.
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assign instr_valid_clear_o = ~(stall | halt_if) | flush_id;
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// update registers
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always_ff @(posedge clk_i or negedge rst_ni) begin : update_regs
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@ -376,7 +376,7 @@ module ibex_id_stage #(
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// Controller //
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////////////////
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assign illegal_insn_o = illegal_insn_dec | illegal_csr_insn_i;
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assign illegal_insn_o = instr_valid_i & (illegal_insn_dec | illegal_csr_insn_i);
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ibex_controller controller_i (
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.clk_i ( clk_i ),
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