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Input signal injection
This commit is contained in:
Flavien Solt
Pirmin Vogel
parent
3a738a2a15
commit
b1ff52dc67
4 changed files with 79 additions and 109 deletions
61
rtl/gift.sv
61
rtl/gift.sv
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@ -37,15 +37,19 @@ module gift (
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logic data_we, key_we;
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// Inter-module signal declaration
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logic [63:0] data_after_middle_rounds;
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logic [127:0] key_after_middle_rounds;
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round_index_e current_round_base;
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// Middle and output modules instantiation
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// Middle module instantiation
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gift_middle_rounds gift_middle_rounds_i (
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.data_i(data_q),
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.key_i(key_q),
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.in_data_i(data_i),
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.in_key_i(key_i),
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.state_data_i(data_q),
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.state_key_i(key_q),
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.round_base_i(current_round_base),
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@ -53,13 +57,6 @@ module gift (
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.key_o(key_after_middle_rounds)
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);
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gift_output_round gift_output_round_i (
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.data_i(data_q),
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.key_i(key_q),
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.data_o(data_o)
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);
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// Flip-flop
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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@ -80,18 +77,13 @@ module gift (
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// FSM
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always_comb begin : gift_cipher_fsm
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// Key management
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key_we = 1'b0;
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key_d = key_q;
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// Data write enable
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// Key and data write enable
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key_we = 1'b0;
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data_we = 1'b0;
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// Stored signals, arbitrarily set by default to the rectangle output
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data_d = data_q;
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// Gift rectangle-specific signals
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current_round_base = BASE_1;
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current_round_base = BASE_INPUT;
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// Handshake signals
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in_ready_o = 1'b0;
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@ -104,10 +96,9 @@ module gift (
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// Take the new key, tweak and data into account
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key_we = 1'b1;
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key_d = key_i;
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data_we = 1'b1;
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data_d = data_i;
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current_round_base = BASE_INPUT;
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// In this state, the cipher is ready to get data
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in_ready_o = 1'b1;
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@ -123,15 +114,9 @@ module gift (
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ROUNDS_INTERNAL_1: begin
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// Key update
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key_we = 1'b1;
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key_d = key_after_middle_rounds;
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data_we = 1'b1;
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// Take middle rounds outputs into account
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data_d = data_after_middle_rounds;
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// Gift rectangle-specific signals
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current_round_base = BASE_1;
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@ -143,13 +128,8 @@ module gift (
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// Key update
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key_we = 1'b1;
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key_d = key_after_middle_rounds;
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data_we = 1'b1;
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// Take middle rounds outputs into account
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data_d = data_after_middle_rounds;
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// Gift rectangle-specific signals
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current_round_base = BASE_2;
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@ -161,13 +141,8 @@ module gift (
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// Key update
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key_we = 1'b1;
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key_d = key_after_middle_rounds;
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data_we = 1'b1;
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// Take middle rounds outputs into account
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data_d = data_after_middle_rounds;
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// Gift rectangle-specific signals
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current_round_base = BASE_3;
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@ -195,18 +170,18 @@ module gift (
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in_ready_o = 1'b1;
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if (in_valid_i) begin
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// Select register input
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current_round_base = BASE_INPUT;
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key_we = 1'b1;
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data_we = 1'b1;
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data_d = data_i;
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key_d = key_i;
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// State transition
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state_d = ROUNDS_INTERNAL_1;
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end else begin
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// Register input does not matter, keep its value
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key_we = 1'b0;
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data_we = 1'b0;
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@ -230,4 +205,8 @@ module gift (
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end
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end
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assign data_d = data_after_middle_rounds;
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assign key_d = key_after_middle_rounds;
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assign data_o = data_q;
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endmodule
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@ -5,8 +5,14 @@
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import gift_pkg::*;
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module gift_middle_rounds (
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input logic [63:0] data_i,
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input logic [127:0] key_i,
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// Data and key coming directly from the cipher input
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input logic [63:0] in_data_i,
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input logic [127:0] in_key_i,
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// Data and key coming from the state register
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input logic [63:0] state_data_i,
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input logic [127:0] state_key_i,
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input round_index_e round_base_i,
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@ -19,41 +25,76 @@ module gift_middle_rounds (
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logic [9:0][63:0] data_states;
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logic [9:0][127:0] key_states;
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logic [8:0][5:0] roundcsts;
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logic [7:0][5:0] roundcsts;
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assign data_states[0] = data_i;
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assign key_states[0] = key_i;
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assign data_states[0] = state_data_i;
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assign key_states[0] = state_key_i;
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// Round constant management
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always_comb begin
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unique case (round_base_i)
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BASE_INPUT: begin
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// The first 4 rounds are not used in this case.
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for (int k = 0; k < 4; k++) begin
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roundcsts[k] = RC[4 + k];
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end
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for (int k = 0; k < 4; k++) begin
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roundcsts[k + 4] = RC[k];
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end
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end
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BASE_1: begin
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for (int k = 0; k < 9; k++) begin
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roundcsts[k] = RC[k];
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for (int k = 0; k < 8; k++) begin
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roundcsts[k] = RC[4 + k];
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end
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end
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BASE_2: begin
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for (int k = 0; k < 9; k++) begin
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roundcsts[k] = RC[9 + k];
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for (int k = 0; k < 8; k++) begin
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roundcsts[k] = RC[12 + k];
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end
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end
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default: begin
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for (int k = 0; k < 9; k++) begin
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roundcsts[k] = RC[18 + k];
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for (int k = 0; k < 8; k++) begin
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roundcsts[k] = RC[20 + k];
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end
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end
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endcase
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end
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// Round instantiation
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for (genvar i = 0; i < 9; i++) begin : gen_rounds
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for (genvar k = 0; k < 4; k++) begin : gen_pre_inject_rounds
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gift_round gift_round_i (
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.data_i(data_states[i]),
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.key_i(key_states[i]),
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.RC_i(roundcsts[i]),
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.data_i(data_states[k]),
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.key_i(key_states[k]),
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.RC_i(roundcsts[k]),
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.data_o(data_states[i+1]),
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.key_o(key_states[i+1])
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.data_o(data_states[k+1]),
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.key_o(key_states[k+1])
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);
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end
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// Input data injection management
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always_comb begin
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unique case (round_base_i)
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BASE_INPUT: begin
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data_states[5] = in_data_i;
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key_states[5] = in_key_i;
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end
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default: begin
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data_states[5] = data_states[4];
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key_states[5] = key_states[4];
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end
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endcase
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end
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for (genvar k = 4; k < 8; k++) begin : gen_post_inject_rounds
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gift_round gift_round_i (
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.data_i(data_states[k + 1]),
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.key_i(key_states[k + 1]),
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.RC_i(roundcsts[k]),
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.data_o(data_states[k + 2]),
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.key_o(key_states[k + 2])
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);
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end
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@ -1,51 +0,0 @@
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module gift_output_round (
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input logic [63:0] data_i,
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input logic [127:0] key_i,
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output logic [63:0] data_o
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);
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import gift_pkg::*;
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logic [63:0] data_after_sbox;
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logic [63:0] data_after_permut;
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logic [63:0] data_after_key;
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logic [63:0] data_state;
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always_comb begin : p_gift_round
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data_state = data_i;
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data_state = sbox_layer(data_state);
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data_after_sbox = data_state;
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data_state = permut_layer(data_after_sbox);
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data_after_permut = data_state;
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// Add round key
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for (int k = 0; k < 16; k++) begin
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data_state[4 * k] ^= key_i[k];
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data_state[4 * k + 1] ^= key_i[k + 16];
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end
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data_after_key = data_state;
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// Add round constant
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data_state[63] ^= 1;
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data_state[23] ^= RC[27][5];
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data_state[19] ^= RC[27][4];
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data_state[15] ^= RC[27][3];
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data_state[11] ^= RC[27][2];
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data_state[7] ^= RC[27][1];
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data_state[3] ^= RC[27][0];
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end
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assign data_o = data_state;
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endmodule
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@ -25,6 +25,7 @@ package gift_pkg;
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};
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typedef enum logic [1:0] {
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BASE_INPUT,
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BASE_1,
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BASE_2,
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BASE_3
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