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https://github.com/lowRISC/ibex.git
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[DV] update ibex log parsing to match new riscv-dv csv format (#547)
Signed-off-by: Udi <udij@google.com>
This commit is contained in:
udinator
GitHub
parent
79bb6c7832
commit
b318b96964
2 changed files with 69 additions and 74 deletions
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@ -13,88 +13,77 @@ sys.path.insert(0, "../../vendor/google_riscv-dv/scripts")
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from riscv_trace_csv import *
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from lib import *
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REGS = ["zero","ra","sp","gp","tp","t0","t1","t2","s0","s1",
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"a0","a1","a2","a3","a4","a5","a6","a7",
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"s2","s3","s4","s5","s6","s7","s8","s9","s10","s11",
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"t3","t4","t5","t6"]
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INSTR_RE = re.compile(r"^\s*(?P<time>\d+)\s+(?P<cycle>\d+)\s+(?P<pc>[0-9a-f]+)\s+" \
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"(?P<bin>[0-9a-f]+)\s+(?P<instr>\S+\s+\S+)\s*")
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RD_RE = re.compile(r"(x(?P<rd>[1-9]\d*)=0x(?P<rd_val>[0-9a-f]+))")
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ADDR_RE = re.compile(r"(?P<imm>[\-0-9]+?)\((?P<rs1>.*)\)")
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def process_ibex_sim_log(ibex_log, csv, full_trace = 1):
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"""Process ibex simulation log.
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"""Process ibex simulation log.
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Extract instruction and affected register information from ibex simulation
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log and save to a standard CSV format.
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"""
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logging.info("Processing ibex log : %s" % ibex_log)
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instr_cnt = 0
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ibex_instr = ""
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Extract instruction and affected register information from ibex simulation
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log and save to a standard CSV format.
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"""
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logging.info("Processing ibex log : %s" % ibex_log)
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instr_cnt = 0
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ibex_instr = ""
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gpr = {}
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for g in REGS:
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gpr[g] = 0
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with open(ibex_log, "r") as f, open(csv, "w") as csv_fd:
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trace_csv = RiscvInstructionTraceCsv(csv_fd)
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trace_csv.start_new_trace()
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for line in f:
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if re.search("ecall", line):
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break
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# Extract instruction information
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m = INSTR_RE.search(line)
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if m:
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instr_cnt += 1
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# Write the extracted instruction to a csvcol buffer file
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rv_instr_trace = RiscvInstructionTraceEntry()
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rv_instr_trace.instr_str = m.group("instr")
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rv_instr_trace.instr = m.group("instr").split()[0]
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rv_instr_trace.pc = m.group("pc")
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rv_instr_trace.binary = m.group("bin")
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if full_trace:
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rv_instr_trace.operand = m.group("instr").split()[1]
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process_trace(rv_instr_trace)
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c = RD_RE.search(line)
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if c:
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rv_instr_trace.gpr.append(gpr_to_abi("x%0s" % c.group("rd")) + ":" + c.group("rd_val"))
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trace_csv.write_trace_entry(rv_instr_trace)
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with open(ibex_log, "r") as f, open(csv, "w") as csv_fd:
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trace_csv = RiscvInstructionTraceCsv(csv_fd)
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trace_csv.start_new_trace()
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for line in f:
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if re.search("ecall", line):
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break
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# Extract instruction information
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m = re.search(r"^\s*(?P<time>\d+)\s+" \
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"(?P<cycle>\d+)\s+" \
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"(?P<pc>[0-9a-f]+)\s+" \
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"(?P<bin>[0-9a-f]+)\s+" \
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"(?P<instr>\S+\s+\S+)\s*" \
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"(x(?P<rs1>\d+):0x(?P<rs1_val>[0-9a-f]+))?\s*" \
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"(x(?P<rs2>\d+):0x(?P<rs2_val>[0-9a-f]+))?\s*" \
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"(x(?P<rd>[1-9]\d*)=0x(?P<rd_val>[0-9a-f]+))", line)
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if m:
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instr_cnt += 1
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# Write the extracted instruction to a csvcol buffer file
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rv_instr_trace = RiscvInstructionTraceEntry()
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rv_instr_trace.rd = gpr_to_abi("x%0s" % m.group("rd"))
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rv_instr_trace.rd_val = m.group("rd_val")
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rv_instr_trace.rs1 = gpr_to_abi("x%0s" % m.group("rs1"))
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rv_instr_trace.rs1_val = m.group("rs1_val")
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rv_instr_trace.rs2 = gpr_to_abi("x%0s" % m.group("rs2"))
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rv_instr_trace.rs2_val = m.group("rs2_val")
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rv_instr_trace.addr = m.group("pc")
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rv_instr_trace.binary = m.group("bin")
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rv_instr_trace.instr_str = m.group("instr")
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rv_instr_trace.instr = rv_instr_trace.instr_str.split()[0]
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logging.info("Processed instruction count : %d" % instr_cnt)
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if instr_cnt == 0:
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logging.error("No instructions in logfile: %s" % ibex_log)
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sys.exit(RET_FATAL)
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logging.info("CSV saved to : %s" % csv)
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# Extract all missing operand values
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if full_trace:
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gpr[rv_instr_trace.rd] = rv_instr_trace.rd_val
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o = re.search(r"(?P<instr_name>[a-z.]*)\s+(?P<operands>.*)", rv_instr_trace.instr_str)
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if o:
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operands = o.group("operands").split(",")
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# Convert to ABI representation
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for i in range(len(operands)):
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abi = re.search(r"(^|\()(?P<gpr>x\d+)", operands[i])
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if abi:
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reg = abi.group("gpr")
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operands[i] = operands[i].replace(reg, gpr_to_abi(reg))
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if rv_instr_trace.instr in ['jalr']:
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# Ibex displays two operands for jalr
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rv_instr_trace.rd = operands[0]
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rv_instr_trace.rd_val = gpr[rv_instr_trace.rd]
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n = ADDR_RE.search(operands[1])
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if n:
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rv_instr_trace.rs1 = n.group("rs1")
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rv_instr_trace.rs1_val = gpr[rv_instr_trace.rs1]
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rv_instr_trace.imm = get_imm_hex_val(n.group("imm"))
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elif rv_instr_trace.instr in ['c.jal']:
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rv_instr_trace.imm = get_imm_hex_val("0x" + operands[0])
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elif rv_instr_trace.instr in ['jal']:
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rv_instr_trace.rd = operands[0]
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rv_instr_trace.rd_val = gpr[rv_instr_trace.rd]
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rv_instr_trace.imm = get_imm_hex_val("0x" + operands[1])
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else:
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assign_operand(rv_instr_trace, operands, gpr)
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trace_csv.write_trace_entry(rv_instr_trace)
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def process_trace(trace):
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""" Process instruction trace """
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process_imm(trace)
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if trace.instr == 'jalr':
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n = ADDR_RE.search(trace.operand)
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if n:
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trace.imm = get_imm_hex_val(n.group("imm"))
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logging.info("Processed instruction count : %d" % instr_cnt)
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def process_imm(trace):
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""" Process imm to follow RISC-V standard convention """
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if trace.instr in ['beq', 'bne', 'blt', 'bge', 'bltu', 'bgeu', 'c.beqz',
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'c.bnez', 'beqz', 'bnez', 'bgez', 'bltz', 'blez', 'bgtz',
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'c.j', 'j', 'c.jal', 'jal']:
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idx = trace.operand.rfind(',')
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if idx == -1:
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imm = trace.operand
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imm = str(sint_to_hex(int(imm, 16) - int(trace.pc, 16)))
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trace.operand = imm
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else:
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imm = trace.operand[idx + 1 : ]
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imm = str(sint_to_hex(int(imm, 16) - int(trace.pc, 16)))
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trace.operand = trace.operand[0 : idx + 1] + imm
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def check_ibex_uvm_log(uvm_log, core_name, test_name, report, write=True):
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@ -20,6 +20,12 @@
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// XLEN
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parameter int XLEN = 32;
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// Vector extension parameters - not used in Ibex
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parameter int VECTOR_EXTENSION_ENABLE = 0;
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parameter int VLEN = 512;
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parameter int ELEN = 64;
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parameter int SLEN = 64;
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// Parameter for SATP mode, set to BARE if address translation is not supported
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parameter satp_mode_t SATP_MODE = BARE;
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