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Update google_riscv-dv to google/riscv-dv@d691906 (#491)

Browse source 
Update code from upstream repository https://github.com/google/riscv-
dv to revision d69190682078470bc6d5661d72f873ae9850ae53

* enable CSR randomization only for csr instructions (google/riscv-
  dv#321) (udinator)
* fix csr test script pathname (Udi Jonnalagadda)

Signed-off-by: Udi <udij@google.com>
This commit is contained in:
udinator 2019-11-22 10:17:24 -08:00 • committed by GitHub
parent 1a2270ce40
commit bb7acbdb7a
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GPG key ID: 4AEE18F83AFDEB23
3 changed files with 21 additions and 18 deletions
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2
vendor/google_riscv-dv.lock.hjson vendored
View file

@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/google/riscv-dv
rev: 39ca85903eea94350d3a610256307346da407e5b
rev: d69190682078470bc6d5661d72f873ae9850ae53
}
}

3
vendor/google_riscv-dv/run.py vendored
View file

@ -146,6 +146,7 @@ def gen(test_list, csr_file, end_signature_addr, isa, simulator,
sim_only : Simulation only
compile_only : Compile the generator only
lsf_cmd : LSF command used to run the instruction generator
cwd : Filesystem path to RISCV-DV repo
seed : Seed to the instruction generator
cmp_opts : Compile options for the generator
sim_opts : Simulation options for the generator
@ -204,7 +205,7 @@ def gen(test_list, csr_file, end_signature_addr, isa, simulator,
to generate directed CSR test code, located at scripts/gen_csr_test.py.
"""
if test['test'] == 'riscv_csr_test':
cmd = "python3 scripts/gen_csr_test.py" + \
cmd = "python3 " + cwd + "/scripts/gen_csr_test.py" + \
(" --csr_file %s" % csr_file) + \
(" --xlen %s" % re.search(r"(?P<xlen>[0-9]+)", isa).group("xlen")) + \
(" --iterations %i" % iterations) + \

34
vendor/google_riscv-dv/src/riscv_rand_instr.sv vendored
View file

@ -98,23 +98,25 @@ class riscv_rand_instr extends riscv_instr_base;
if(cfg.no_csr_instr) {
category != CSR;
} else {
if (cfg.enable_illegal_csr_instruction) {
!(csr inside {implemented_csr});
} else if (cfg.enable_access_invalid_csr_level) {
csr inside {cfg.invalid_priv_mode_csrs};
} else {
// Use scratch register to avoid the side effect of modifying other privileged mode CSR.
if (cfg.init_privileged_mode == MACHINE_MODE) {
if (MSCRATCH inside {implemented_csr}) {
csr == MSCRATCH;
}
} else if (cfg.init_privileged_mode == SUPERVISOR_MODE) {
if (SSCRATCH inside {implemented_csr}) {
csr == SSCRATCH;
}
if (category == CSR) {
if (cfg.enable_illegal_csr_instruction) {
!(csr inside {implemented_csr});
} else if (cfg.enable_access_invalid_csr_level) {
csr inside {cfg.invalid_priv_mode_csrs};
} else {
if (USCRATCH inside {implemented_csr}) {
csr == USCRATCH;
// Use scratch register to avoid the side effect of modifying other privileged mode CSR.
if (cfg.init_privileged_mode == MACHINE_MODE) {
if (MSCRATCH inside {implemented_csr}) {
csr == MSCRATCH;
}
} else if (cfg.init_privileged_mode == SUPERVISOR_MODE) {
if (SSCRATCH inside {implemented_csr}) {
csr == SSCRATCH;
}
} else {
if (USCRATCH inside {implemented_csr}) {
csr == USCRATCH;
}
}
}
}