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https://github.com/lowRISC/ibex.git
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[style] Fix whitespace issues around operators
Our style guide typically require a single whitespace around operators.
This commit is contained in:
Philipp Wagner
Philipp Wagner
parent
b5011ecec6
commit
be27bc8bcf
17 changed files with 96 additions and 96 deletions
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@ -67,10 +67,10 @@ module prim_badbit_ram_1p #(
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// Similarly, extend addr, wdata, wmask and sram_rdata (the un-fiddled value)
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logic [31:0] addr;
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logic [127:0] wdata, wmask, rdata;
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assign addr = {{32-Aw{1'b0}}, addr_i};
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assign wdata = {{128-Width{1'b0}}, wdata_i};
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assign wmask = {{128-Width{1'b0}}, wmask_i};
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assign rdata = {{128-Width{1'b0}}, sram_rdata};
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assign addr = {{32 - Aw{1'b0}}, addr_i};
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assign wdata = {{128 - Width{1'b0}}, wdata_i};
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assign wmask = {{128 - Width{1'b0}}, wmask_i};
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assign rdata = {{128 - Width{1'b0}}, sram_rdata};
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// To inject errors, bind in an interface with bad_bit_mask as an output and assign one of the
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// bits in bad_bit_mask[Width-1:0] to one. The wired-OR together with an assignment to zero means
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@ -75,10 +75,10 @@ module ibex_alu #(
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// prepare operand b
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assign operand_b_neg = {operand_b_i,1'b0} ^ {33{1'b1}};
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always_comb begin
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unique case(1'b1)
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unique case (1'b1)
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multdiv_sel_i: adder_in_b = multdiv_operand_b_i;
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adder_op_b_negate: adder_in_b = operand_b_neg;
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default : adder_in_b = {operand_b_i, 1'b0};
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default: adder_in_b = {operand_b_i, 1'b0};
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endcase
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end
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@ -248,7 +248,7 @@ module ibex_alu #(
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assign bfp_len = {~(|operand_b_i[27:24]), operand_b_i[27:24]}; // len = 0 encodes for len = 16
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assign bfp_off = operand_b_i[20:16];
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assign bfp_mask = (RV32B != RV32BNone) ? ~(32'hffff_ffff << bfp_len) : '0;
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for (genvar i=0; i<32; i++) begin : gen_rev_bfp_mask
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for (genvar i = 0; i < 32; i++) begin : gen_rev_bfp_mask
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assign bfp_mask_rev[i] = bfp_mask[31-i];
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end
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@ -262,7 +262,7 @@ module ibex_alu #(
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always_comb begin
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if (bfp_op) begin
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shift_amt[4:0] = bfp_off ; // length field of bfp control word
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shift_amt[4:0] = bfp_off; // length field of bfp control word
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end else begin
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shift_amt[4:0] = instr_first_cycle_i ?
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(operand_b_i[5] && shift_funnel ? shift_amt_compl[4:0] : operand_b_i[4:0]) :
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@ -327,7 +327,7 @@ module ibex_alu #(
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shift_result = shift_result_ext[31:0];
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unused_shift_result_ext = shift_result_ext[32];
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for (int unsigned i=0; i<32; i++) begin
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for (int unsigned i = 0; i < 32; i++) begin
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shift_result_rev[i] = shift_result[31-i];
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end
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@ -436,7 +436,7 @@ module ibex_alu #(
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assign zbe_op = (operator_i == ALU_BEXT) | (operator_i == ALU_BDEP);
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always_comb begin
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case(1'b1)
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case (1'b1)
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zbe_op: bitcnt_bits = operand_b_i;
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bitcnt_cz: bitcnt_bits = bitcnt_bit_mask & ~bitcnt_mask_op; // clz / ctz
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default: bitcnt_bits = operand_a_i; // pcnt
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@ -487,19 +487,19 @@ module ibex_alu #(
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always_comb begin
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bitcnt_partial = '{default: '0};
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// stage 1
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for (int unsigned i=1; i<32; i+=2) begin
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for (int unsigned i = 1; i < 32; i += 2) begin
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bitcnt_partial[i] = {5'h0, bitcnt_bits[i]} + {5'h0, bitcnt_bits[i-1]};
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end
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// stage 2
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for (int unsigned i=3; i<32; i+=4) begin
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for (int unsigned i = 3; i < 32; i += 4) begin
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bitcnt_partial[i] = bitcnt_partial[i-2] + bitcnt_partial[i];
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end
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// stage 3
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for (int unsigned i=7; i<32; i+=8) begin
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for (int unsigned i = 7; i < 32; i += 8) begin
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bitcnt_partial[i] = bitcnt_partial[i-4] + bitcnt_partial[i];
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end
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// stage 4
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for (int unsigned i=15; i <32; i+=16) begin
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for (int unsigned i = 15; i < 32; i += 16) begin
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bitcnt_partial[i] = bitcnt_partial[i-8] + bitcnt_partial[i];
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end
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// stage 5
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@ -510,17 +510,17 @@ module ibex_alu #(
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bitcnt_partial[23] = bitcnt_partial[15] + bitcnt_partial[23];
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// stage 6
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for (int unsigned i=11; i<32; i+=8) begin
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for (int unsigned i = 11; i < 32; i += 8) begin
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bitcnt_partial[i] = bitcnt_partial[i-4] + bitcnt_partial[i];
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end
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// stage 7
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for (int unsigned i=5; i<32; i+=4) begin
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for (int unsigned i = 5; i < 32; i += 4) begin
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bitcnt_partial[i] = bitcnt_partial[i-2] + bitcnt_partial[i];
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end
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// stage 8
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bitcnt_partial[0] = {5'h0, bitcnt_bits[0]};
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for (int unsigned i=2; i<32; i+=2) begin
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for (int unsigned i = 2; i < 32; i += 2) begin
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bitcnt_partial[i] = bitcnt_partial[i-1] + {5'h0, bitcnt_bits[i]};
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end
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end
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@ -761,23 +761,23 @@ module ibex_alu #(
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// first cycle
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// Store partial bitcnts
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for (genvar i=0; i<32; i++) begin : gen_bitcnt_reg_in_lsb
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for (genvar i = 0; i < 32; i++) begin : gen_bitcnt_reg_in_lsb
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assign bitcnt_partial_lsb_d[i] = bitcnt_partial[i][0];
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end
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for (genvar i=0; i<16; i++) begin : gen_bitcnt_reg_in_b1
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for (genvar i = 0; i < 16; i++) begin : gen_bitcnt_reg_in_b1
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assign bitcnt_partial_msb_d[i] = bitcnt_partial[2*i+1][1];
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end
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for (genvar i=0; i<8; i++) begin : gen_bitcnt_reg_in_b2
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for (genvar i = 0; i < 8; i++) begin : gen_bitcnt_reg_in_b2
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assign bitcnt_partial_msb_d[16+i] = bitcnt_partial[4*i+3][2];
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end
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for (genvar i=0; i<4; i++) begin : gen_bitcnt_reg_in_b3
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for (genvar i = 0; i < 4; i++) begin : gen_bitcnt_reg_in_b3
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assign bitcnt_partial_msb_d[24+i] = bitcnt_partial[8*i+7][3];
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end
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for (genvar i=0; i<2; i++) begin : gen_bitcnt_reg_in_b4
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for (genvar i = 0; i < 2; i++) begin : gen_bitcnt_reg_in_b4
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assign bitcnt_partial_msb_d[28+i] = bitcnt_partial[16*i+15][4];
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end
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@ -789,23 +789,23 @@ module ibex_alu #(
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always_comb begin
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bitcnt_partial_q = '{default: '0};
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for (int unsigned i=0; i<32; i++) begin : gen_bitcnt_reg_out_lsb
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for (int unsigned i = 0; i < 32; i++) begin : gen_bitcnt_reg_out_lsb
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bitcnt_partial_q[i][0] = imd_val_q_i[0][i];
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end
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for (int unsigned i=0; i<16; i++) begin : gen_bitcnt_reg_out_b1
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for (int unsigned i = 0; i < 16; i++) begin : gen_bitcnt_reg_out_b1
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bitcnt_partial_q[2*i+1][1] = imd_val_q_i[1][i];
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end
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for (int unsigned i=0; i<8; i++) begin : gen_bitcnt_reg_out_b2
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for (int unsigned i = 0; i < 8; i++) begin : gen_bitcnt_reg_out_b2
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bitcnt_partial_q[4*i+3][2] = imd_val_q_i[1][16+i];
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end
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for (int unsigned i=0; i<4; i++) begin : gen_bitcnt_reg_out_b3
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for (int unsigned i = 0; i < 4; i++) begin : gen_bitcnt_reg_out_b3
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bitcnt_partial_q[8*i+7][3] = imd_val_q_i[1][24+i];
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end
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for (int unsigned i=0; i<2; i++) begin : gen_bitcnt_reg_out_b4
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for (int unsigned i = 0; i < 2; i++) begin : gen_bitcnt_reg_out_b4
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bitcnt_partial_q[16*i+15][4] = imd_val_q_i[1][28+i];
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end
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@ -821,7 +821,7 @@ module ibex_alu #(
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`define _N(stg) (16 >> stg)
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// bext / bdep control bit generation
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for (genvar stg=0; stg<5; stg++) begin : gen_butterfly_ctrl_stage
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for (genvar stg = 0; stg < 5; stg++) begin : gen_butterfly_ctrl_stage
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// number of segs: 2** stg
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for (genvar seg=0; seg<2**stg; seg++) begin : gen_butterfly_ctrl
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@ -841,7 +841,7 @@ module ibex_alu #(
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end
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`undef _N
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for (genvar stg=0; stg<5; stg++) begin : gen_butterfly_not
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for (genvar stg = 0; stg < 5; stg++) begin : gen_butterfly_not
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assign butterfly_mask_not[stg] =
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~(butterfly_mask_l[stg] | butterfly_mask_r[stg]);
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end
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@ -970,7 +970,7 @@ module ibex_alu #(
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logic [31:0] clmul_result_raw;
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for (genvar i=0; i<32; i++) begin: gen_rev_operand_b
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for (genvar i = 0; i < 32; i++) begin : gen_rev_operand_b
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assign operand_b_rev[i] = operand_b_i[31-i];
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end
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@ -1007,7 +1007,7 @@ module ibex_alu #(
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assign crc_mu_rev = crc_cpoly ? CRC32C_MU_REV : CRC32_MU_REV;
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always_comb begin
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unique case(1'b1)
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unique case (1'b1)
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crc_bmode: crc_operand = {operand_a_i[7:0], 24'h0};
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crc_hmode: crc_operand = {operand_a_i[15:0], 16'h0};
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default: crc_operand = operand_a_i;
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@ -1025,36 +1025,36 @@ module ibex_alu #(
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end
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end
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for (genvar i=0; i<32; i++) begin : gen_clmul_and_op
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for (genvar i = 0; i < 32; i++) begin : gen_clmul_and_op
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assign clmul_and_stage[i] = clmul_op_b[i] ? clmul_op_a << i : '0;
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end
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for (genvar i=0; i<16; i++) begin : gen_clmul_xor_op_l1
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for (genvar i = 0; i < 16; i++) begin : gen_clmul_xor_op_l1
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assign clmul_xor_stage1[i] = clmul_and_stage[2*i] ^ clmul_and_stage[2*i+1];
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end
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for (genvar i=0; i<8; i++) begin : gen_clmul_xor_op_l2
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for (genvar i = 0; i < 8; i++) begin : gen_clmul_xor_op_l2
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assign clmul_xor_stage2[i] = clmul_xor_stage1[2*i] ^ clmul_xor_stage1[2*i+1];
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end
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for (genvar i=0; i<4; i++) begin : gen_clmul_xor_op_l3
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for (genvar i = 0; i < 4; i++) begin : gen_clmul_xor_op_l3
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assign clmul_xor_stage3[i] = clmul_xor_stage2[2*i] ^ clmul_xor_stage2[2*i+1];
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end
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for (genvar i=0; i<2; i++) begin : gen_clmul_xor_op_l4
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for (genvar i = 0; i < 2; i++) begin : gen_clmul_xor_op_l4
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assign clmul_xor_stage4[i] = clmul_xor_stage3[2*i] ^ clmul_xor_stage3[2*i+1];
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end
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assign clmul_result_raw = clmul_xor_stage4[0] ^ clmul_xor_stage4[1];
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for (genvar i=0; i<32; i++) begin : gen_rev_clmul_result
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for (genvar i = 0; i < 32; i++) begin : gen_rev_clmul_result
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assign clmul_result_rev[i] = clmul_result_raw[31-i];
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end
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// clmulr_result = rev(clmul(rev(a), rev(b)))
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// clmulh_result = clmulr_result >> 1
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always_comb begin
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case(1'b1)
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case (1'b1)
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clmul_rmode: clmul_result = clmul_result_rev;
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clmul_hmode: clmul_result = {1'b0, clmul_result_rev[31:1]};
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default: clmul_result = clmul_result_raw;
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@ -1123,7 +1123,7 @@ module ibex_alu #(
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ALU_CRC32_H, ALU_CRC32C_H,
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ALU_CRC32_B, ALU_CRC32C_B: begin
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if (RV32B == RV32BFull) begin
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unique case(1'b1)
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unique case (1'b1)
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crc_bmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 8);
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crc_hmode: multicycle_result = clmul_result_rev ^ (operand_a_i >> 16);
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default: multicycle_result = clmul_result_rev;
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@ -229,7 +229,7 @@ module ibex_compressed_decoder (
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end else begin
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// c.jr -> jalr x0, rd/rs1, 0
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instr_o = {12'b0, instr_i[11:7], 3'b0, 5'b0, {OPCODE_JALR}};
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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if (instr_i[11:7] == 5'b0) illegal_instr_o = 1'b1;
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end
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end else begin
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if (instr_i[6:2] != 5'b0) begin
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@ -691,8 +691,8 @@ module ibex_controller #(
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// Exception/fault prioritisation logic will have set exactly 1 X_prio signal
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unique case (1'b1)
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instr_fetch_err_prio: begin
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exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT;
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csr_mtval_o = instr_fetch_err_plus2_i ? (pc_id_i + 32'd2) : pc_id_i;
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exc_cause_o = EXC_CAUSE_INSTR_ACCESS_FAULT;
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csr_mtval_o = instr_fetch_err_plus2_i ? (pc_id_i + 32'd2) : pc_id_i;
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end
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illegal_insn_prio: begin
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exc_cause_o = EXC_CAUSE_ILLEGAL_INSN;
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@ -1173,7 +1173,7 @@ module ibex_core import ibex_pkg::*; #(
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assign rvfi_instr_new_wb = instr_new_id;
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end
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for (genvar i = 0;i < RVFI_STAGES; i = i + 1) begin : g_rvfi_stages
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for (genvar i = 0; i < RVFI_STAGES; i = i + 1) begin : g_rvfi_stages
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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rvfi_stage_halt[i] <= '0;
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@ -1203,7 +1203,7 @@ module ibex_core import ibex_pkg::*; #(
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rvfi_stage_valid[i] <= rvfi_stage_valid_d[i];
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if (i == 0) begin
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if(instr_id_done) begin
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if (instr_id_done) begin
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rvfi_stage_halt[i] <= '0;
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rvfi_stage_trap[i] <= illegal_insn_id;
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rvfi_stage_intr[i] <= rvfi_intr_d;
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@ -1228,7 +1228,7 @@ module ibex_core import ibex_pkg::*; #(
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rvfi_stage_mem_addr[i] <= rvfi_mem_addr_d;
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end
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end else begin
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if(instr_done_wb) begin
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if (instr_done_wb) begin
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rvfi_stage_halt[i] <= rvfi_stage_halt[i-1];
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rvfi_stage_trap[i] <= rvfi_stage_trap[i-1];
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rvfi_stage_intr[i] <= rvfi_stage_intr[i-1];
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@ -1347,16 +1347,16 @@ module ibex_core import ibex_pkg::*; #(
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end
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always_comb begin
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if(rvfi_rd_we_wb) begin
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if (rvfi_rd_we_wb) begin
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// Capture address/data of write to register file
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rvfi_rd_addr_d = rvfi_rd_addr_wb;
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rvfi_rd_addr_d = rvfi_rd_addr_wb;
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// If writing to x0 zero write data as required by RVFI specification
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if(rvfi_rd_addr_wb == 5'b0) begin
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if (rvfi_rd_addr_wb == 5'b0) begin
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rvfi_rd_wdata_d = '0;
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end else begin
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rvfi_rd_wdata_d = rvfi_rd_wdata_wb;
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end
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end else if(rvfi_instr_new_wb) begin
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end else if (rvfi_instr_new_wb) begin
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// If no RF write but new instruction in Writeback (when present) or ID/EX (when no writeback
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// stage present) then zero RF write address/data as required by RVFI specification
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rvfi_rd_addr_d = '0;
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@ -30,12 +30,12 @@ module ibex_counter #(
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end
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// Increment
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counter_upd = counter[CounterWidth-1:0] + {{CounterWidth-1{1'b0}},1'b1};
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counter_upd = counter[CounterWidth-1:0] + {{CounterWidth - 1{1'b0}}, 1'b1};
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// Next value logic
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if (we) begin
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counter_d = counter_load[CounterWidth-1:0];
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end else if (counter_inc_i)begin
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end else if (counter_inc_i) begin
|
||||
counter_d = counter_upd[CounterWidth-1:0];
|
||||
end else begin
|
||||
counter_d = counter[CounterWidth-1:0];
|
||||
|
|
@ -44,7 +44,7 @@ module ibex_counter #(
|
|||
|
||||
`ifdef FPGA_XILINX
|
||||
// Set DSP pragma for supported xilinx FPGAs
|
||||
localparam int DspPragma = CounterWidth < 49 ? "yes" : "no";
|
||||
localparam int DspPragma = CounterWidth < 49 ? "yes" : "no";
|
||||
(* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q;
|
||||
|
||||
// DSP output register requires synchronous reset.
|
||||
|
|
|
|||
|
|
@ -476,7 +476,7 @@ module ibex_cs_registers #(
|
|||
|
||||
// Custom CSR for controlling CPU features
|
||||
CSR_CPUCTRL: begin
|
||||
csr_rdata_int = {{32-$bits(cpu_ctrl_t){1'b0}},cpuctrl_q};
|
||||
csr_rdata_int = {{32 - $bits(cpu_ctrl_t) {1'b0}}, cpuctrl_q};
|
||||
end
|
||||
|
||||
// Custom CSR for LFSR re-seeding (cannot be read)
|
||||
|
|
@ -1018,7 +1018,7 @@ module ibex_cs_registers #(
|
|||
// For G >= 2, bits are masked to one or zero depending on the mode
|
||||
always_comb begin
|
||||
// In NAPOT mode, bits [G-2:0] must read as one
|
||||
pmp_addr_rdata[i] = {pmp_addr[i], {PMPGranularity-1{1'b1}}};
|
||||
pmp_addr_rdata[i] = {pmp_addr[i], {PMPGranularity - 1{1'b1}}};
|
||||
|
||||
if ((pmp_cfg[i].mode == PMP_MODE_OFF) || (pmp_cfg[i].mode == PMP_MODE_TOR)) begin
|
||||
// In TOR or OFF mode, bits [G-1:0] must read as zero
|
||||
|
|
@ -1172,7 +1172,7 @@ module ibex_cs_registers #(
|
|||
always_comb begin : gen_mhpmcounter_incr
|
||||
|
||||
// Assign inactive counters (first to prevent latch inference)
|
||||
for (int unsigned i=0; i<32; i++) begin : gen_mhpmcounter_incr_inactive
|
||||
for (int unsigned i = 0; i < 32; i++) begin : gen_mhpmcounter_incr_inactive
|
||||
mhpmcounter_incr[i] = 1'b0;
|
||||
end
|
||||
|
||||
|
|
@ -1200,14 +1200,14 @@ module ibex_cs_registers #(
|
|||
always_comb begin : gen_mhpmevent
|
||||
|
||||
// activate all
|
||||
for (int i=0; i<32; i++) begin : gen_mhpmevent_active
|
||||
for (int i = 0; i < 32; i++) begin : gen_mhpmevent_active
|
||||
mhpmevent[i] = '0;
|
||||
mhpmevent[i][i] = 1'b1;
|
||||
end
|
||||
|
||||
// deactivate
|
||||
mhpmevent[1] = '0; // not existing, reserved
|
||||
for (int unsigned i=3+MHPMCounterNum; i<32; i++) begin : gen_mhpmevent_inactive
|
||||
for (int unsigned i = 3 + MHPMCounterNum; i < 32; i++) begin : gen_mhpmevent_inactive
|
||||
mhpmevent[i] = '0;
|
||||
end
|
||||
end
|
||||
|
|
@ -1244,7 +1244,7 @@ module ibex_cs_registers #(
|
|||
assign unused_mhpmcounterh_we_1 = mhpmcounterh_we[1];
|
||||
assign unused_mhpmcounter_incr_1 = mhpmcounter_incr[1];
|
||||
|
||||
for (genvar cnt=0; cnt < 29; cnt++) begin : gen_cntrs
|
||||
for (genvar cnt = 0; cnt < 29; cnt++) begin : gen_cntrs
|
||||
if (cnt < MHPMCounterNum) begin : gen_imp
|
||||
ibex_counter #(
|
||||
.CounterWidth(MHPMCounterWidth)
|
||||
|
|
@ -1262,12 +1262,12 @@ module ibex_cs_registers #(
|
|||
end
|
||||
end
|
||||
|
||||
if(MHPMCounterNum < 29) begin : g_mcountinhibit_reduced
|
||||
if (MHPMCounterNum < 29) begin : g_mcountinhibit_reduced
|
||||
logic [29-MHPMCounterNum-1:0] unused_mhphcounter_we;
|
||||
logic [29-MHPMCounterNum-1:0] unused_mhphcounterh_we;
|
||||
logic [29-MHPMCounterNum-1:0] unused_mhphcounter_incr;
|
||||
|
||||
assign mcountinhibit = {{29-MHPMCounterNum{1'b1}}, mcountinhibit_q};
|
||||
assign mcountinhibit = {{29 - MHPMCounterNum{1'b1}}, mcountinhibit_q};
|
||||
// Lint tieoffs for unused bits
|
||||
assign unused_mhphcounter_we = mhpmcounter_we[31:MHPMCounterNum+3];
|
||||
assign unused_mhphcounterh_we = mhpmcounterh_we[31:MHPMCounterNum+3];
|
||||
|
|
|
|||
|
|
@ -116,31 +116,31 @@ module ibex_dummy_instr import ibex_pkg::*; #(
|
|||
// Encode instruction
|
||||
always_comb begin
|
||||
unique case (lfsr_data.instr_type)
|
||||
DUMMY_ADD : begin
|
||||
DUMMY_ADD: begin
|
||||
dummy_set = 7'b0000000;
|
||||
dummy_opcode = 3'b000;
|
||||
end
|
||||
DUMMY_MUL : begin
|
||||
DUMMY_MUL: begin
|
||||
dummy_set = 7'b0000001;
|
||||
dummy_opcode = 3'b000;
|
||||
end
|
||||
DUMMY_DIV : begin
|
||||
DUMMY_DIV: begin
|
||||
dummy_set = 7'b0000001;
|
||||
dummy_opcode = 3'b100;
|
||||
end
|
||||
DUMMY_AND : begin
|
||||
DUMMY_AND: begin
|
||||
dummy_set = 7'b0000000;
|
||||
dummy_opcode = 3'b111;
|
||||
end
|
||||
default : begin
|
||||
default: begin
|
||||
dummy_set = 7'b0000000;
|
||||
dummy_opcode = 3'b000;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
// SET RS2 RS1 OP RD
|
||||
assign dummy_instr = {dummy_set,lfsr_data.op_b,lfsr_data.op_a,dummy_opcode,5'h00,7'h33};
|
||||
// SET RS2 RS1 OP RD
|
||||
assign dummy_instr = {dummy_set, lfsr_data.op_b, lfsr_data.op_a, dummy_opcode, 5'h00, 7'h33};
|
||||
|
||||
// Assign outputs
|
||||
assign insert_dummy_instr_o = insert_dummy_instr;
|
||||
|
|
|
|||
|
|
@ -590,7 +590,7 @@ module ibex_icache import ibex_pkg::*; #(
|
|||
fb_fill_level = '0;
|
||||
for (int i = 0; i < NUM_FB; i++) begin
|
||||
if (fill_busy_q[i] & ~fill_stale_q[i]) begin
|
||||
fb_fill_level += {{$clog2(NUM_FB)-1{1'b0}},1'b1};
|
||||
fb_fill_level += {{$clog2(NUM_FB) - 1{1'b0}}, 1'b1};
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -1103,7 +1103,7 @@ module ibex_icache import ibex_pkg::*; #(
|
|||
|
||||
always_comb begin
|
||||
output_data_hi = '0;
|
||||
for (int i = 0; i < IC_OUTPUT_BEATS-1; i++) begin
|
||||
for (int i = 0; i < IC_OUTPUT_BEATS - 1; i++) begin
|
||||
if (output_addr_q[BUS_W-1:1] == i[BUS_W-2:0]) begin
|
||||
output_data_hi |= output_data[(i+1)*16+:16];
|
||||
end
|
||||
|
|
|
|||
|
|
@ -388,7 +388,7 @@ module ibex_id_stage #(
|
|||
// Multicycle Operation Stage Register //
|
||||
/////////////////////////////////////////
|
||||
|
||||
for (genvar i=0; i<2; i++) begin : gen_intermediate_val_reg
|
||||
for (genvar i = 0; i < 2; i++) begin : gen_intermediate_val_reg
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin : intermediate_val_reg
|
||||
if (!rst_ni) begin
|
||||
imd_val_q[i] <= '0;
|
||||
|
|
|
|||
|
|
@ -190,13 +190,13 @@ module ibex_lockstep import ibex_pkg::*; #(
|
|||
data_rdata_intg_q <= '0;
|
||||
for (int unsigned i = 0; i < LockstepOffset; i++) begin
|
||||
shadow_inputs_q[i] <= delayed_inputs_t'('0);
|
||||
shadow_tag_rdata_q[i] <= '{default:0};
|
||||
shadow_data_rdata_q[i] <= '{default:0};
|
||||
shadow_tag_rdata_q[i] <= '{default: 0};
|
||||
shadow_data_rdata_q[i] <= '{default: 0};
|
||||
end
|
||||
end else begin
|
||||
instr_rdata_intg_q <= instr_rdata_intg_i;
|
||||
data_rdata_intg_q <= data_rdata_intg_i;
|
||||
for (int unsigned i = 0; i < LockstepOffset-1; i++) begin
|
||||
for (int unsigned i = 0; i < LockstepOffset - 1; i++) begin
|
||||
shadow_inputs_q[i] <= shadow_inputs_q[i+1];
|
||||
shadow_tag_rdata_q[i] <= shadow_tag_rdata_q[i+1];
|
||||
shadow_data_rdata_q[i] <= shadow_data_rdata_q[i+1];
|
||||
|
|
@ -302,7 +302,7 @@ module ibex_lockstep import ibex_pkg::*; #(
|
|||
|
||||
// Delay the outputs
|
||||
always_ff @(posedge clk_i) begin
|
||||
for (int unsigned i = 0; i < OutputsOffset-1; i++) begin
|
||||
for (int unsigned i = 0; i < OutputsOffset - 1; i++) begin
|
||||
core_outputs_q[i] <= core_outputs_q[i+1];
|
||||
end
|
||||
core_outputs_q[OutputsOffset-1] <= core_outputs_in;
|
||||
|
|
|
|||
|
|
@ -415,7 +415,7 @@ module ibex_multdiv_fast #(
|
|||
div_hold = 1'b0;
|
||||
div_by_zero_d = div_by_zero_q;
|
||||
|
||||
unique case(md_state_q)
|
||||
unique case (md_state_q)
|
||||
MD_IDLE: begin
|
||||
if (operator_i == MD_OP_DIV) begin
|
||||
// Check if the Denominator is 0
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@ module ibex_multdiv_slow
|
|||
always_comb begin
|
||||
alu_operand_a_o = accum_window_q;
|
||||
|
||||
unique case(operator_i)
|
||||
unique case (operator_i)
|
||||
|
||||
MD_OP_MULL: begin
|
||||
alu_operand_b_o = op_a_bw_pp;
|
||||
|
|
@ -108,7 +108,7 @@ module ibex_multdiv_slow
|
|||
|
||||
MD_OP_DIV,
|
||||
MD_OP_REM: begin
|
||||
unique case(md_state_q)
|
||||
unique case (md_state_q)
|
||||
MD_IDLE: begin
|
||||
// 0 - B = 0 iff B == 0
|
||||
alu_operand_a_o = {32'h0 , 1'b1};
|
||||
|
|
@ -181,9 +181,9 @@ module ibex_multdiv_slow
|
|||
multdiv_hold = 1'b0;
|
||||
div_by_zero_d = div_by_zero_q;
|
||||
if (mult_sel_i || div_sel_i) begin
|
||||
unique case(md_state_q)
|
||||
unique case (md_state_q)
|
||||
MD_IDLE: begin
|
||||
unique case(operator_i)
|
||||
unique case (operator_i)
|
||||
MD_OP_MULL: begin
|
||||
op_a_shift_d = op_a_ext << 1;
|
||||
accum_window_d = { ~(op_a_ext[32] & op_b_i[0]),
|
||||
|
|
@ -233,15 +233,15 @@ module ibex_multdiv_slow
|
|||
|
||||
MD_ABS_B: begin
|
||||
// remainder
|
||||
accum_window_d = {32'h0,op_numerator_q[31]};
|
||||
accum_window_d = {32'h0, op_numerator_q[31]};
|
||||
// B abs value
|
||||
op_b_shift_d = sign_b ? {1'b0,alu_adder_i} : {1'b0,op_b_i};
|
||||
op_b_shift_d = sign_b ? {1'b0, alu_adder_i} : {1'b0, op_b_i};
|
||||
md_state_d = MD_COMP;
|
||||
end
|
||||
|
||||
MD_COMP: begin
|
||||
multdiv_count_d = multdiv_count_q - 5'h1;
|
||||
unique case(operator_i)
|
||||
unique case (operator_i)
|
||||
MD_OP_MULL: begin
|
||||
accum_window_d = res_adder_l;
|
||||
op_a_shift_d = op_a_shift_q << 1;
|
||||
|
|
@ -268,7 +268,7 @@ module ibex_multdiv_slow
|
|||
end
|
||||
|
||||
MD_LAST: begin
|
||||
unique case(operator_i)
|
||||
unique case (operator_i)
|
||||
MD_OP_MULL: begin
|
||||
accum_window_d = res_adder_l;
|
||||
|
||||
|
|
@ -301,7 +301,7 @@ module ibex_multdiv_slow
|
|||
|
||||
MD_CHANGE_SIGN: begin
|
||||
md_state_d = MD_FINISH;
|
||||
unique case(operator_i)
|
||||
unique case (operator_i)
|
||||
MD_OP_DIV:
|
||||
accum_window_d = div_change_sign ? {1'b0,alu_adder_i} : accum_window_q;
|
||||
MD_OP_REM:
|
||||
|
|
|
|||
|
|
@ -56,7 +56,7 @@ module ibex_pmp #(
|
|||
csr_pmp_addr_i[r];
|
||||
end
|
||||
// Address mask for NA matching
|
||||
for (genvar b = PMPGranularity+2; b < 34; b++) begin : g_bitmask
|
||||
for (genvar b = PMPGranularity + 2; b < 34; b++) begin : g_bitmask
|
||||
if (b == 2) begin : g_bit0
|
||||
// Always mask bit 2 for NAPOT
|
||||
assign region_addr_mask[r][b] = (csr_pmp_cfg_i[r].mode != PMP_MODE_NAPOT);
|
||||
|
|
@ -92,14 +92,14 @@ module ibex_pmp #(
|
|||
always_comb begin
|
||||
region_match_all[c][r] = 1'b0;
|
||||
unique case (csr_pmp_cfg_i[r].mode)
|
||||
PMP_MODE_OFF : region_match_all[c][r] = 1'b0;
|
||||
PMP_MODE_NA4 : region_match_all[c][r] = region_match_eq[c][r];
|
||||
PMP_MODE_NAPOT : region_match_all[c][r] = region_match_eq[c][r];
|
||||
PMP_MODE_TOR : begin
|
||||
PMP_MODE_OFF: region_match_all[c][r] = 1'b0;
|
||||
PMP_MODE_NA4: region_match_all[c][r] = region_match_eq[c][r];
|
||||
PMP_MODE_NAPOT: region_match_all[c][r] = region_match_eq[c][r];
|
||||
PMP_MODE_TOR: begin
|
||||
region_match_all[c][r] = (region_match_eq[c][r] | region_match_gt[c][r]) &
|
||||
region_match_lt[c][r];
|
||||
end
|
||||
default : region_match_all[c][r] = 1'b0;
|
||||
default: region_match_all[c][r] = 1'b0;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
|
@ -156,7 +156,7 @@ module ibex_pmp #(
|
|||
|
||||
// PMP entries are statically prioritized, from 0 to N-1
|
||||
// The lowest-numbered PMP entry which matches an address determines accessability
|
||||
for (int r = PMPNumRegions-1; r >= 0; r--) begin
|
||||
for (int r = PMPNumRegions - 1; r >= 0; r--) begin
|
||||
if (region_match_all[c][r]) begin
|
||||
if (csr_pmp_mseccfg_i.mml) begin
|
||||
// When MSECCFG.MML is set use MML specific permission check
|
||||
|
|
|
|||
|
|
@ -47,7 +47,7 @@ module ibex_register_file_ff #(
|
|||
|
||||
always_comb begin : we_a_decoder
|
||||
for (int unsigned i = 1; i < NUM_WORDS; i++) begin
|
||||
we_a_dec[i] = (waddr_a_i == 5'(i)) ? we_a_i : 1'b0;
|
||||
we_a_dec[i] = (waddr_a_i == 5'(i)) ? we_a_i : 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -56,7 +56,7 @@ module ibex_register_file_ff #(
|
|||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
rf_reg_q[i] <= '0;
|
||||
end else if(we_a_dec[i]) begin
|
||||
end else if (we_a_dec[i]) begin
|
||||
rf_reg_q[i] <= wdata_a_i;
|
||||
end
|
||||
end
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ module ibex_register_file_fpga #(
|
|||
);
|
||||
|
||||
localparam int ADDR_WIDTH = RV32E ? 4 : 5;
|
||||
localparam int NUM_WORDS = 2**ADDR_WIDTH;
|
||||
localparam int NUM_WORDS = 2 ** ADDR_WIDTH;
|
||||
|
||||
logic [DataWidth-1:0] mem[NUM_WORDS];
|
||||
logic we; // write enable if writing to any register other than R0
|
||||
|
|
|
|||
|
|
@ -61,7 +61,7 @@ module ibex_wb_stage #(
|
|||
logic [31:0] rf_wdata_wb_mux [2];
|
||||
logic [1:0] rf_wdata_wb_mux_we;
|
||||
|
||||
if(WritebackStage) begin : g_writeback_stage
|
||||
if (WritebackStage) begin : g_writeback_stage
|
||||
logic [31:0] rf_wdata_wb_q;
|
||||
logic rf_we_wb_q;
|
||||
logic [4:0] rf_waddr_wb_q;
|
||||
|
|
@ -86,7 +86,7 @@ module ibex_wb_stage #(
|
|||
assign wb_done = (wb_instr_type_q == WB_INSTR_OTHER) | lsu_resp_valid_i;
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if(~rst_ni) begin
|
||||
if (~rst_ni) begin
|
||||
wb_valid_q <= 1'b0;
|
||||
end else begin
|
||||
wb_valid_q <= wb_valid_d;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue